nco.map.qmsg

使用QUARTUS 2编译的DDS的源码

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LPM_ROM sinlup:U_sinlup\|romtab:U_romtab\|LPM_ROM:LPM_ROM_component " "Info: Elaborating entity \"LPM_ROM\" for hierarchy \"sinlup:U_sinlup\|romtab:U_romtab\|LPM_ROM:LPM_ROM_component\"" {  } { { "romtab.vhd" "LPM_ROM_component" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/romtab.vhd" 49 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus51/libraries/megafunctions/altrom.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/altrom.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altrom " "Info: Found entity 1: altrom" {  } { { "altrom.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/altrom.tdf" 75 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altrom sinlup:U_sinlup\|romtab:U_romtab\|LPM_ROM:LPM_ROM_component\|altrom:srom " "Info: Elaborating entity \"altrom\" for hierarchy \"sinlup:U_sinlup\|romtab:U_romtab\|LPM_ROM:LPM_ROM_component\|altrom:srom\"" {  } { { "LPM_ROM.tdf" "srom" { Text "d:/altera/quartus51/libraries/megafunctions/LPM_ROM.tdf" 52 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "sinlup:U_sinlup\|romtab:U_romtab\|LPM_ROM:LPM_ROM_component\|altrom:srom sinlup:U_sinlup\|romtab:U_romtab\|LPM_ROM:LPM_ROM_component " "Info: Issued messages during elaboration of megafunction \"sinlup:U_sinlup\|romtab:U_romtab\|LPM_ROM:LPM_ROM_component\|altrom:srom\", which is child of megafunction \"sinlup:U_sinlup\|romtab:U_romtab\|LPM_ROM:LPM_ROM_component\"" {  } { { "LPM_ROM.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/LPM_ROM.tdf" 52 3 0 } } { "romtab.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/romtab.vhd" 49 -1 0 } }  } 0 0 "Issued messages during elaboration of megafunction \"%1!s!\", which is child of megafunction \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sinlup:U_sinlup\|romtab:U_romtab\|LPM_ROM:LPM_ROM_component " "Info: Instantiated megafunction \"sinlup:U_sinlup\|romtab:U_romtab\|LPM_ROM:LPM_ROM_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 7 " "Info: Parameter \"LPM_WIDTH\" = \"7\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHAD 6 " "Info: Parameter \"LPM_WIDTHAD\" = \"6\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_ADDRESS_CONTROL REGISTERED " "Info: Parameter \"LPM_ADDRESS_CONTROL\" = \"REGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_INDATA REGISTERED " "Info: Parameter \"LPM_INDATA\" = \"REGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_OUTDATA UNREGISTERED " "Info: Parameter \"LPM_OUTDATA\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_FILE G:\\\\test\\\\quartus\\\\NCO\\\\ncosin.mif " "Info: Parameter \"LPM_FILE\" = \"G:\\\\test\\\\quartus\\\\NCO\\\\ncosin.mif\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" " constraint(address) 5 downto 0 " "Info: Parameter \" constraint(address)\" = \"5 downto 0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" " constraint(q) 6 downto 0 " "Info: Parameter \" constraint(q)\" = \"6 downto 0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "romtab.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/romtab.vhd" 49 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Warning" "WTDFX_ASSERTION" "altrom does not support Stratix device family -- attempting best-case memory conversions, but power-up states will be different for Stratix devices " "Warning: Assertion warning: altrom does not support Stratix device family -- attempting best-case memory conversions, but power-up states will be different for Stratix devices" {  } { { "altrom.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/altrom.tdf" 173 2 0 } } { "LPM_ROM.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/LPM_ROM.tdf" 52 3 0 } } { "romtab.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/romtab.vhd" 49 -1 0 } } { "sinlup.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/sinlup.vhd" 42 -1 0 } } { "nco.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/nco.vhd" 76 -1 0 } }  } 0 0 "Assertion warning: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus51/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram sinlup:U_sinlup\|romtab:U_romtab\|LPM_ROM:LPM_ROM_component\|altrom:srom\|altsyncram:rom_block " "Info: Elaborating entity \"altsyncram\" for hierarchy \"sinlup:U_sinlup\|romtab:U_romtab\|LPM_ROM:LPM_ROM_component\|altrom:srom\|altsyncram:rom_block\"" {  } { { "altrom.tdf" "rom_block" { Text "d:/altera/quartus51/libraries/megafunctions/altrom.tdf" 88 7 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_86r.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_86r.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_86r " "Info: Found entity 1: altsyncram_86r" {  } { { "db/altsyncram_86r.tdf" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/altsyncram_86r.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_86r sinlup:U_sinlup\|romtab:U_romtab\|LPM_ROM:LPM_ROM_component\|altrom:srom\|altsyncram:rom_block\|altsyncram_86r:auto_generated " "Info: Elaborating entity \"altsyncram_86r\" for hierarchy \"sinlup:U_sinlup\|romtab:U_romtab\|LPM_ROM:LPM_ROM_component\|altrom:srom\|altsyncram:rom_block\|altsyncram_86r:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Critical Warning" "WCDB_CDB_FILE_NOT_FOUND" "G:/test/quartus/NCO/ncosin.mif " "Critical Warning: Can't find Memory Initialization File or Hexadecimal (Intel-Format) File G:/test/quartus/NCO/ncosin.mif -- setting all initial values to 0" {  } { { "db/altsyncram_86r.tdf" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/altsyncram_86r.tdf" 43 2 0 } }  } 1 0 "Can't find Memory Initialization File or Hexadecimal (Intel-Format) File %1!s! -- setting all initial values to 0" 0 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "3 " "Info: Ignored 3 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "3 " "Info: Ignored 3 SOFT buffer(s)" {  } {  } 0 0 "Ignored %1!d! SOFT buffer(s)" 0 0}  } {  } 0 0 "Ignored %1!d! buffer(s)" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR_HDR" "" "Warning: Converted TRI buffer or tri-state bus to logic, or removed OPNDRN" { { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "sinlup:U_sinlup\|romtab:U_romtab\|lpm_rom:LPM_ROM_component\|otri\[6\] " "Warning: Converting TRI node \"sinlup:U_sinlup\|romtab:U_romtab\|lpm_rom:LPM_ROM_component\|otri\[6\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/LPM_ROM.tdf" 65 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "sinlup:U_sinlup\|romtab:U_romtab\|lpm_rom:LPM_ROM_component\|otri\[5\] " "Warning: Converting TRI node \"sinlup:U_sinlup\|romtab:U_romtab\|lpm_rom:LPM_ROM_component\|otri\[5\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/LPM_ROM.tdf" 65 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "sinlup:U_sinlup\|romtab:U_romtab\|lpm_rom:LPM_ROM_component\|otri\[4\] " "Warning: Converting TRI node \"sinlup:U_sinlup\|romtab:U_romtab\|lpm_rom:LPM_ROM_component\|otri\[4\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/LPM_ROM.tdf" 65 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "sinlup:U_sinlup\|romtab:U_romtab\|lpm_rom:LPM_ROM_component\|otri\[3\] " "Warning: Converting TRI node \"sinlup:U_sinlup\|romtab:U_romtab\|lpm_rom:LPM_ROM_component\|otri\[3\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/LPM_ROM.tdf" 65 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "sinlup:U_sinlup\|romtab:U_romtab\|lpm_rom:LPM_ROM_component\|otri\[2\] " "Warning: Converting TRI node \"sinlup:U_sinlup\|romtab:U_romtab\|lpm_rom:LPM_ROM_component\|otri\[2\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/LPM_ROM.tdf" 65 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "sinlup:U_sinlup\|romtab:U_romtab\|lpm_rom:LPM_ROM_component\|otri\[1\] " "Warning: Converting TRI node \"sinlup:U_sinlup\|romtab:U_romtab\|lpm_rom:LPM_ROM_component\|otri\[1\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/LPM_ROM.tdf" 65 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "sinlup:U_sinlup\|romtab:U_romtab\|lpm_rom:LPM_ROM_component\|otri\[0\] " "Warning: Converting TRI node \"sinlup:U_sinlup\|romtab:U_romtab\|lpm_rom:LPM_ROM_component\|otri\[0\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/LPM_ROM.tdf" 65 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0}  } {  } 0 0 "Converted TRI buffer or tri-state bus to logic, or removed OPNDRN" 0 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "3 " "Info: Ignored 3 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "3 " "Info: Ignored 3 SOFT buffer(s)" {  } {  } 0 0 "Ignored %1!d! SOFT buffer(s)" 0 0}  } {  } 0 0 "Ignored %1!d! buffer(s)" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "226 " "Info: Implemented 226 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "44 " "Info: Implemented 44 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "12 " "Info: Implemented 12 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "163 " "Info: Implemented 163 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_RAMS" "7 " "Info: Implemented 7 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 21 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 21 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 12 22:37:45 2006 " "Info: Processing ended: Tue Dec 12 22:37:45 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}