nco.map.qmsg

使用QUARTUS 2编译的DDS的源码

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_csnbuffer phasea:U_phasea\|lpm_add_sub:lpm_add_1\|addcore:adder\|a_csnbuffer:oflow_node " "Info: Elaborating entity \"a_csnbuffer\" for hierarchy \"phasea:U_phasea\|lpm_add_sub:lpm_add_1\|addcore:adder\|a_csnbuffer:oflow_node\"" {  } { { "addcore.tdf" "oflow_node" { Text "d:/altera/quartus51/libraries/megafunctions/addcore.tdf" 94 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_csnbuffer phasea:U_phasea\|lpm_add_sub:lpm_add_1\|addcore:adder\|a_csnbuffer:result_node " "Info: Elaborating entity \"a_csnbuffer\" for hierarchy \"phasea:U_phasea\|lpm_add_sub:lpm_add_1\|addcore:adder\|a_csnbuffer:result_node\"" {  } { { "addcore.tdf" "result_node" { Text "d:/altera/quartus51/libraries/megafunctions/addcore.tdf" 120 6 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus51/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altshift phasea:U_phasea\|lpm_add_sub:lpm_add_1\|altshift:result_ext_latency_ffs " "Info: Elaborating entity \"altshift\" for hierarchy \"phasea:U_phasea\|lpm_add_sub:lpm_add_1\|altshift:result_ext_latency_ffs\"" {  } { { "lpm_add_sub.tdf" "result_ext_latency_ffs" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 284 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altshift phasea:U_phasea\|lpm_add_sub:lpm_add_1\|altshift:carry_ext_latency_ffs " "Info: Elaborating entity \"altshift\" for hierarchy \"phasea:U_phasea\|lpm_add_sub:lpm_add_1\|altshift:carry_ext_latency_ffs\"" {  } { { "lpm_add_sub.tdf" "carry_ext_latency_ffs" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 286 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub phasea:U_phasea\|lpm_add_sub:lpm_add_2 " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"phasea:U_phasea\|lpm_add_sub:lpm_add_2\"" {  } { { "phasea.vhd" "lpm_add_2" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/phasea.vhd" 62 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub phasea:U_phasea\|lpm_add_sub:lpm_add_4 " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"phasea:U_phasea\|lpm_add_sub:lpm_add_4\"" {  } { { "phasea.vhd" "lpm_add_4" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/phasea.vhd" 68 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "addcore phasea:U_phasea\|lpm_add_sub:lpm_add_4\|addcore:adder " "Info: Elaborating entity \"addcore\" for hierarchy \"phasea:U_phasea\|lpm_add_sub:lpm_add_4\|addcore:adder\"" {  } { { "lpm_add_sub.tdf" "adder" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 266 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "phasemod.vhd 2 1 " "Warning: Using design file phasemod.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 phasemod-Phmodul " "Info: Found design unit 1: phasemod-Phmodul" {  } { { "phasemod.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/phasemod.vhd" 30 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 phasemod " "Info: Found entity 1: phasemod" {  } { { "phasemod.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/phasemod.vhd" 18 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "phasemod phasemod:U_phasemod " "Info: Elaborating entity \"phasemod\" for hierarchy \"phasemod:U_phasemod\"" {  } { { "nco.vhd" "U_phasemod" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/nco.vhd" 75 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "c phasemod.vhd(34) " "Warning (10036): Verilog HDL or VHDL warning at phasemod.vhd(34): object \"c\" assigned a value but never read" {  } { { "phasemod.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/phasemod.vhd" 34 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub phasemod:U_phasemod\|lpm_add_sub:Adder " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"phasemod:U_phasemod\|lpm_add_sub:Adder\"" {  } { { "phasemod.vhd" "Adder" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/phasemod.vhd" 50 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "sinlup.vhd 2 1 " "Warning: Using design file sinlup.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sinlup-sinlook " "Info: Found design unit 1: sinlup-sinlook" {  } { { "sinlup.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/sinlup.vhd" 27 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sinlup " "Info: Found entity 1: sinlup" {  } { { "sinlup.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/sinlup.vhd" 18 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sinlup sinlup:U_sinlup " "Info: Elaborating entity \"sinlup\" for hierarchy \"sinlup:U_sinlup\"" {  } { { "nco.vhd" "U_sinlup" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/nco.vhd" 76 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "romtab.vhd 2 1 " "Warning: Using design file romtab.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 romtab-ROM " "Info: Found design unit 1: romtab-ROM" {  } { { "romtab.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/romtab.vhd" 26 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 romtab " "Info: Found entity 1: romtab" {  } { { "romtab.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/romtab.vhd" 18 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "romtab sinlup:U_sinlup\|romtab:U_romtab " "Info: Elaborating entity \"romtab\" for hierarchy \"sinlup:U_sinlup\|romtab:U_romtab\"" {  } { { "sinlup.vhd" "U_romtab" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/sinlup.vhd" 42 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus51/libraries/megafunctions/LPM_ROM.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/LPM_ROM.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_rom " "Info: Found entity 1: lpm_rom" {  } { { "LPM_ROM.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/LPM_ROM.tdf" 41 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}