nco.map.qmsg

使用QUARTUS 2编译的DDS的源码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 12 22:37:39 2006 " "Info: Processing started: Tue Dec 12 22:37:39 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off nco -c nco " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off nco -c nco" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "nco.vhd 2 1 " "Warning: Using design file nco.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 NCO-top " "Info: Found design unit 1: NCO-top" {  } { { "nco.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/nco.vhd" 31 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 NCO " "Info: Found entity 1: NCO" {  } { { "nco.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/nco.vhd" 15 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "nco " "Info: Elaborating entity \"nco\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "loadfw.vhd 2 1 " "Warning: Using design file loadfw.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 loadfw-Load " "Info: Found design unit 1: loadfw-Load" {  } { { "loadfw.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/loadfw.vhd" 28 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 loadfw " "Info: Found entity 1: loadfw" {  } { { "loadfw.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/loadfw.vhd" 18 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "loadfw loadfw:U_loadfw " "Info: Elaborating entity \"loadfw\" for hierarchy \"loadfw:U_loadfw\"" {  } { { "nco.vhd" "U_loadfw" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/nco.vhd" 72 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "FREQWORD loadfw.vhd(43) " "Warning (10492): VHDL Process Statement warning at loadfw.vhd(43): signal \"FREQWORD\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "loadfw.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/loadfw.vhd" 43 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "loadpw.vhd 2 1 " "Warning: Using design file loadpw.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 loadpw-Load " "Info: Found design unit 1: loadpw-Load" {  } { { "loadpw.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/loadpw.vhd" 26 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 loadpw " "Info: Found entity 1: loadpw" {  } { { "loadpw.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/loadpw.vhd" 16 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "loadpw loadpw:U_loadpw " "Info: Elaborating entity \"loadpw\" for hierarchy \"loadpw:U_loadpw\"" {  } { { "nco.vhd" "U_loadpw" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/nco.vhd" 73 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "PHASEWORD loadpw.vhd(41) " "Warning (10492): VHDL Process Statement warning at loadpw.vhd(41): signal \"PHASEWORD\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "loadpw.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/loadpw.vhd" 41 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "phasea.vhd 2 1 " "Warning: Using design file phasea.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 phasea-Accum " "Info: Found design unit 1: phasea-Accum" {  } { { "phasea.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/phasea.vhd" 32 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 phasea " "Info: Found entity 1: phasea" {  } { { "phasea.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/phasea.vhd" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "phasea phasea:U_phasea " "Info: Elaborating entity \"phasea\" for hierarchy \"phasea:U_phasea\"" {  } { { "nco.vhd" "U_phasea" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/nco.vhd" 74 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "c4 phasea.vhd(41) " "Warning (10036): Verilog HDL or VHDL warning at phasea.vhd(41): object \"c4\" assigned a value but never read" {  } { { "phasea.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/phasea.vhd" 41 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub phasea:U_phasea\|lpm_add_sub:lpm_add_1 " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"phasea:U_phasea\|lpm_add_sub:lpm_add_1\"" {  } { { "phasea.vhd" "lpm_add_1" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/phasea.vhd" 59 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus51/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "addcore phasea:U_phasea\|lpm_add_sub:lpm_add_1\|addcore:adder " "Info: Elaborating entity \"addcore\" for hierarchy \"phasea:U_phasea\|lpm_add_sub:lpm_add_1\|addcore:adder\"" {  } { { "lpm_add_sub.tdf" "adder" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 266 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}