nco.map.eqn

使用QUARTUS 2编译的DDS的源码

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--D1_pipe4[6] is phasea:U_phasea|pipe4[6]
--operation mode is arithmetic

D1_pipe4[6]_carry_eqn = D1L42;
D1_pipe4[6]_lut_out = D1_pipe4[6] $ B1_pipefw4[6] $ D1_pipe4[6]_carry_eqn;
D1_pipe4[6] = DFFEAS(D1_pipe4[6]_lut_out, SYSCLK, VCC, , , , , RESETN, );

--D1L44 is phasea:U_phasea|pipe4[6]~95
--operation mode is arithmetic

D1L44 = CARRY(D1_pipe4[6] & !B1_pipefw4[6] & !D1L42 # !D1_pipe4[6] & (!D1L42 # !B1_pipefw4[6]));


--D1_pipe4[7] is phasea:U_phasea|pipe4[7]
--operation mode is normal

D1_pipe4[7]_carry_eqn = D1L44;
D1_pipe4[7]_lut_out = D1_pipe4[7] $ B1_pipefw4[7] $ !D1_pipe4[7]_carry_eqn;
D1_pipe4[7] = DFFEAS(D1_pipe4[7]_lut_out, SYSCLK, VCC, , , , , RESETN, );


--D1L1 is phasea:U_phasea|COS~0
--operation mode is normal

D1L1 = D1_pipe4[6] $ D1_pipe4[7];


--E1_mphsreg[6] is phasemod:U_phasemod|mphsreg[6]
--operation mode is arithmetic

E1_mphsreg[6]_carry_eqn = E1L14;
E1_mphsreg[6]_lut_out = D1_pipe4[6] $ C1_phswd[6] $ !E1_mphsreg[6]_carry_eqn;
E1_mphsreg[6] = DFFEAS(E1_mphsreg[6]_lut_out, SYSCLK, VCC, , , , , RESETN, );

--E1L16 is phasemod:U_phasemod|mphsreg[6]~89
--operation mode is arithmetic

E1L16 = CARRY(D1_pipe4[6] & (C1_phswd[6] # !E1L14) # !D1_pipe4[6] & C1_phswd[6] & !E1L14);


--E1_mphsreg[7] is phasemod:U_phasemod|mphsreg[7]
--operation mode is normal

E1_mphsreg[7]_carry_eqn = E1L16;
E1_mphsreg[7]_lut_out = D1_pipe4[7] $ C1_phswd[7] $ E1_mphsreg[7]_carry_eqn;
E1_mphsreg[7] = DFFEAS(E1_mphsreg[7]_lut_out, SYSCLK, VCC, , , , , RESETN, );


--E1L1 is phasemod:U_phasemod|MCOS~0
--operation mode is normal

E1L1 = E1_mphsreg[6] $ E1_mphsreg[7];


--F1_NCOOUT[0] is sinlup:U_sinlup|NCOOUT[0]
--operation mode is normal

F1_NCOOUT[0]_lut_out = F1_qwavesin_ff[0];
F1_NCOOUT[0] = DFFEAS(F1_NCOOUT[0]_lut_out, SYSCLK, VCC, , , , , RESETN, );


--F1_NCOOUT[1] is sinlup:U_sinlup|NCOOUT[1]
--operation mode is normal

F1_NCOOUT[1]_lut_out = F1_modphase_msb3_ff & (F1L1) # !F1_modphase_msb3_ff & F1_qwavesin_ff[1];
F1_NCOOUT[1] = DFFEAS(F1_NCOOUT[1]_lut_out, SYSCLK, VCC, , , , , RESETN, );


--F1_NCOOUT[2] is sinlup:U_sinlup|NCOOUT[2]
--operation mode is normal

F1_NCOOUT[2]_lut_out = F1_modphase_msb3_ff & (F1L3) # !F1_modphase_msb3_ff & F1_qwavesin_ff[2];
F1_NCOOUT[2] = DFFEAS(F1_NCOOUT[2]_lut_out, SYSCLK, VCC, , , , , RESETN, );


--F1_NCOOUT[3] is sinlup:U_sinlup|NCOOUT[3]
--operation mode is normal

F1_NCOOUT[3]_lut_out = F1_modphase_msb3_ff & (F1L5) # !F1_modphase_msb3_ff & F1_qwavesin_ff[3];
F1_NCOOUT[3] = DFFEAS(F1_NCOOUT[3]_lut_out, SYSCLK, VCC, , , , , RESETN, );


--F1_NCOOUT[4] is sinlup:U_sinlup|NCOOUT[4]
--operation mode is normal

F1_NCOOUT[4]_lut_out = F1_modphase_msb3_ff & (F1L7) # !F1_modphase_msb3_ff & F1_qwavesin_ff[4];
F1_NCOOUT[4] = DFFEAS(F1_NCOOUT[4]_lut_out, SYSCLK, VCC, , , , , RESETN, );


--F1_NCOOUT[5] is sinlup:U_sinlup|NCOOUT[5]
--operation mode is normal

F1_NCOOUT[5]_lut_out = F1_modphase_msb3_ff & (F1L9) # !F1_modphase_msb3_ff & F1_qwavesin_ff[5];
F1_NCOOUT[5] = DFFEAS(F1_NCOOUT[5]_lut_out, SYSCLK, VCC, , , , , RESETN, );


--F1_NCOOUT[6] is sinlup:U_sinlup|NCOOUT[6]
--operation mode is normal

F1_NCOOUT[6]_lut_out = F1_modphase_msb3_ff & (F1L11) # !F1_modphase_msb3_ff & F1_qwavesin_ff[6];
F1_NCOOUT[6] = DFFEAS(F1_NCOOUT[6]_lut_out, SYSCLK, VCC, , , , , RESETN, );


--F1_NCOOUT[7] is sinlup:U_sinlup|NCOOUT[7]
--operation mode is normal

F1_NCOOUT[7]_lut_out = F1_modphase_msb3_ff & (!RESETN);
F1_NCOOUT[7] = DFFEAS(F1_NCOOUT[7]_lut_out, SYSCLK, VCC, , , , , , );


--B1_pipefw4[6] is loadfw:U_loadfw|pipefw4[6]
--operation mode is normal

B1_pipefw4[6]_lut_out = FREQWORD[30] & (!RESETN);
B1_pipefw4[6] = DFFEAS(B1_pipefw4[6]_lut_out, SYSCLK, VCC, , B1L41, , , , );


--D1_pipe4[5] is phasea:U_phasea|pipe4[5]
--operation mode is arithmetic

D1_pipe4[5]_carry_eqn = D1L40;
D1_pipe4[5]_lut_out = D1_pipe4[5] $ B1_pipefw4[5] $ !D1_pipe4[5]_carry_eqn;
D1_pipe4[5] = DFFEAS(D1_pipe4[5]_lut_out, SYSCLK, VCC, , , , , RESETN, );

--D1L42 is phasea:U_phasea|pipe4[5]~103
--operation mode is arithmetic

D1L42 = CARRY(D1_pipe4[5] & (B1_pipefw4[5] # !D1L40) # !D1_pipe4[5] & B1_pipefw4[5] & !D1L40);


--B1_pipefw4[7] is loadfw:U_loadfw|pipefw4[7]
--operation mode is normal

B1_pipefw4[7]_lut_out = FREQWORD[31] & (!RESETN);
B1_pipefw4[7] = DFFEAS(B1_pipefw4[7]_lut_out, SYSCLK, VCC, , B1L41, , , , );


--C1_phswd[6] is loadpw:U_loadpw|phswd[6]
--operation mode is normal

C1_phswd[6]_lut_out = PHASEWORD[6] & (!RESETN);
C1_phswd[6] = DFFEAS(C1_phswd[6]_lut_out, SYSCLK, VCC, , C1L10, , , , );


--E1_mphsreg[5] is phasemod:U_phasemod|mphsreg[5]
--operation mode is arithmetic

E1_mphsreg[5]_carry_eqn = E1L12;
E1_mphsreg[5]_lut_out = D1_pipe4[5] $ C1_phswd[5] $ E1_mphsreg[5]_carry_eqn;
E1_mphsreg[5] = DFFEAS(E1_mphsreg[5]_lut_out, SYSCLK, VCC, , , , , RESETN, );

--E1L14 is phasemod:U_phasemod|mphsreg[5]~97
--operation mode is arithmetic

E1L14 = CARRY(D1_pipe4[5] & !C1_phswd[5] & !E1L12 # !D1_pipe4[5] & (!E1L12 # !C1_phswd[5]));


--C1_phswd[7] is loadpw:U_loadpw|phswd[7]
--operation mode is normal

C1_phswd[7]_lut_out = PHASEWORD[7] & (!RESETN);
C1_phswd[7] = DFFEAS(C1_phswd[7]_lut_out, SYSCLK, VCC, , C1L10, , , , );


--F1_qwavesin_ff[0] is sinlup:U_sinlup|qwavesin_ff[0]
--operation mode is normal

F1_qwavesin_ff[0]_lut_out = Q1_q_a[0] & (!RESETN);
F1_qwavesin_ff[0] = DFFEAS(F1_qwavesin_ff[0]_lut_out, SYSCLK, VCC, , , , , , );


--F1_qwavesin_ff[1] is sinlup:U_sinlup|qwavesin_ff[1]
--operation mode is normal

F1_qwavesin_ff[1]_lut_out = Q1_q_a[1] & (!RESETN);
F1_qwavesin_ff[1] = DFFEAS(F1_qwavesin_ff[1]_lut_out, SYSCLK, VCC, , , , , , );


--F1L1 is sinlup:U_sinlup|add~106
--operation mode is arithmetic

F1L1_carry_eqn = F1L13;
F1L1 = F1_qwavesin_ff[1] $ (!F1L1_carry_eqn);

--F1L2 is sinlup:U_sinlup|add~108
--operation mode is arithmetic

F1L2 = CARRY(F1_qwavesin_ff[1] # !F1L13);


--F1_modphase_msb3_ff is sinlup:U_sinlup|modphase_msb3_ff
--operation mode is normal

F1_modphase_msb3_ff_lut_out = F1_modphase_msb2_ff;
F1_modphase_msb3_ff = DFFEAS(F1_modphase_msb3_ff_lut_out, SYSCLK, VCC, , !RESETN, , , , );


--F1_qwavesin_ff[2] is sinlup:U_sinlup|qwavesin_ff[2]
--operation mode is normal

F1_qwavesin_ff[2]_lut_out = Q1_q_a[2] & (!RESETN);
F1_qwavesin_ff[2] = DFFEAS(F1_qwavesin_ff[2]_lut_out, SYSCLK, VCC, , , , , , );


--F1L3 is sinlup:U_sinlup|add~111
--operation mode is arithmetic

F1L3_carry_eqn = F1L2;
F1L3 = F1_qwavesin_ff[2] $ (F1L3_carry_eqn);

--F1L4 is sinlup:U_sinlup|add~113
--operation mode is arithmetic

F1L4 = CARRY(!F1_qwavesin_ff[2] & (!F1L2));


--F1_qwavesin_ff[3] is sinlup:U_sinlup|qwavesin_ff[3]
--operation mode is normal

F1_qwavesin_ff[3]_lut_out = Q1_q_a[3] & (!RESETN);
F1_qwavesin_ff[3] = DFFEAS(F1_qwavesin_ff[3]_lut_out, SYSCLK, VCC, , , , , , );


--F1L5 is sinlup:U_sinlup|add~116
--operation mode is arithmetic

F1L5_carry_eqn = F1L4;
F1L5 = F1_qwavesin_ff[3] $ (!F1L5_carry_eqn);

--F1L6 is sinlup:U_sinlup|add~118
--operation mode is arithmetic

F1L6 = CARRY(F1_qwavesin_ff[3] # !F1L4);


--F1_qwavesin_ff[4] is sinlup:U_sinlup|qwavesin_ff[4]
--operation mode is normal

F1_qwavesin_ff[4]_lut_out = Q1_q_a[4] & (!RESETN);
F1_qwavesin_ff[4] = DFFEAS(F1_qwavesin_ff[4]_lut_out, SYSCLK, VCC, , , , , , );


--F1L7 is sinlup:U_sinlup|add~121
--operation mode is arithmetic

F1L7_carry_eqn = F1L6;
F1L7 = F1_qwavesin_ff[4] $ (F1L7_carry_eqn);

--F1L8 is sinlup:U_sinlup|add~123
--operation mode is arithmetic

F1L8 = CARRY(!F1_qwavesin_ff[4] & (!F1L6));


--F1_qwavesin_ff[5] is sinlup:U_sinlup|qwavesin_ff[5]
--operation mode is normal

F1_qwavesin_ff[5]_lut_out = Q1_q_a[5] & (!RESETN);
F1_qwavesin_ff[5] = DFFEAS(F1_qwavesin_ff[5]_lut_out, SYSCLK, VCC, , , , , , );


--F1L9 is sinlup:U_sinlup|add~126
--operation mode is arithmetic

F1L9_carry_eqn = F1L8;
F1L9 = F1_qwavesin_ff[5] $ (!F1L9_carry_eqn);

--F1L10 is sinlup:U_sinlup|add~128
--operation mode is arithmetic

F1L10 = CARRY(F1_qwavesin_ff[5] # !F1L8);


--F1_qwavesin_ff[6] is sinlup:U_sinlup|qwavesin_ff[6]
--operation mode is normal

F1_qwavesin_ff[6]_lut_out = Q1_q_a[6] & (!RESETN);
F1_qwavesin_ff[6] = DFFEAS(F1_qwavesin_ff[6]_lut_out, SYSCLK, VCC, , , , , , );


--F1L11 is sinlup:U_sinlup|add~131
--operation mode is normal

F1L11_carry_eqn = F1L10;
F1L11 = F1_qwavesin_ff[6] $ (F1L11_carry_eqn);


--B1_loadp4 is loadfw:U_loadfw|loadp4
--operation mode is normal

B1_loadp4_lut_out = B1_loadp3 & (!RESETN);
B1_loadp4 = DFFEAS(B1_loadp4_lut_out, SYSCLK, VCC, , , , , , );


--B1L41 is loadfw:U_loadfw|pipefw4[2]~133
--operation mode is normal

B1L41 = RESETN # B1_loadp4;


--B1_pipefw4[5] is loadfw:U_loadfw|pipefw4[5]
--operation mode is normal

B1_pipefw4[5]_lut_out = FREQWORD[29] & (!RESETN);
B1_pipefw4[5] = DFFEAS(B1_pipefw4[5]_lut_out, SYSCLK, VCC, , B1L41, , , , );


--D1_pipe4[4] is phasea:U_phasea|pipe4[4]
--operation mode is arithmetic

D1_pipe4[4]_carry_eqn = D1L38;
D1_pipe4[4]_lut_out = D1_pipe4[4] $ B1_pipefw4[4] $ D1_pipe4[4]_carry_eqn;
D1_pipe4[4] = DFFEAS(D1_pipe4[4]_lut_out, SYSCLK, VCC, , , , , RESETN, );

--D1L40 is phasea:U_phasea|pipe4[4]~107
--operation mode is arithmetic

D1L40 = CARRY(D1_pipe4[4] & !B1_pipefw4[4] & !D1L38 # !D1_pipe4[4] & (!D1L38 # !B1_pipefw4[4]));


--C1_load is loadpw:U_loadpw|load
--operation mode is normal

C1_load_lut_out = !C1_pwwrns & C1_pwwrnm;
C1_load = DFFEAS(C1_load_lut_out, SYSCLK, VCC, , , , , RESETN, );


--C1L10 is loadpw:U_loadpw|phswd[6]~133
--operation mode is normal

C1L10 = C1_load # RESETN;


--C1_phswd[5] is loadpw:U_loadpw|phswd[5]
--operation mode is normal

C1_phswd[5]_lut_out = PHASEWORD[5] & (!RESETN);
C1_phswd[5] = DFFEAS(C1_phswd[5]_lut_out, SYSCLK, VCC, , C1L10, , , , );


--E1_mphsreg[4] is phasemod:U_phasemod|mphsreg[4]
--operation mode is arithmetic

E1_mphsreg[4]_carry_eqn = E1L10;
E1_mphsreg[4]_lut_out = D1_pipe4[4] $ C1_phswd[4] $ !E1_mphsreg[4]_carry_eqn;
E1_mphsreg[4] = DFFEAS(E1_mphsreg[4]_lut_out, SYSCLK, VCC, , , , , RESETN, );

--E1L12 is phasemod:U_phasemod|mphsreg[4]~101
--operation mode is arithmetic

E1L12 = CARRY(D1_pipe4[4] & (C1_phswd[4] # !E1L10) # !D1_pipe4[4] & C1_phswd[4] & !E1L10);


--Q1_q_a[0] is sinlup:U_sinlup|romtab:U_romtab|lpm_rom:LPM_ROM_component|altrom:srom|altsyncram:rom_block|altsyncram_86r:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 64, Port A Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 7
--Port A Input: Registered, Port A Output: Un-registered
Q1_q_a[0]_PORT_A_address = BUS(F1_phaseadd[0], F1_phaseadd[1], F1_phaseadd[2], F1_phaseadd[3], F1_phaseadd[4], F1_phaseadd[5]);
Q1_q_a[0]_PORT_A_address_reg = DFFE(Q1_q_a[0]_PORT_A_address, Q1_q_a[0]_clock_0, , , );
Q1_q_a[0]_clock_0 = SYSCLK;
Q1_q_a[0]_PORT_A_data_out = MEMORY(, , Q1_q_a[0]_PORT_A_address_reg, , , , , , Q1_q_a[0]_clock_0, , , , , );
Q1_q_a[0] = Q1_q_a[0]_PORT_A_data_out[0];


--Q1_q_a[1] is sinlup:U_sinlup|romtab:U_romtab|lpm_rom:LPM_ROM_component|altrom:srom|altsyncram:rom_block|altsyncram_86r:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 64, Port A Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 7
--Port A Input: Registered, Port A Output: Un-registered
Q1_q_a[1]_PORT_A_address = BUS(F1_phaseadd[0], F1_phaseadd[1], F1_phaseadd[2], F1_phaseadd[3], F1_phaseadd[4], F1_phaseadd[5]);
Q1_q_a[1]_PORT_A_address_reg = DFFE(Q1_q_a[1]_PORT_A_address, Q1_q_a[1]_clock_0, , , );
Q1_q_a[1]_clock_0 = SYSCLK;
Q1_q_a[1]_PORT_A_data_out = MEMORY(, , Q1_q_a[1]_PORT_A_address_reg, , , , , , Q1_q_a[1]_clock_0, , , , , );
Q1_q_a[1] = Q1_q_a[1]_PORT_A_data_out[0];


--F1L13 is sinlup:U_sinlup|add~138
--operation mode is arithmetic

F1L13 = CARRY(!F1_qwavesin_ff[0]);


--F1_modphase_msb2_ff is sinlup:U_sinlup|modphase_msb2_ff
--operation mode is normal

F1_modphase_msb2_ff_lut_out = F1_modphase_msb1_ff & (!RESETN);
F1_modphase_msb2_ff = DFFEAS(F1_modphase_msb2_ff_lut_out, SYSCLK, VCC, , , , , , );


--Q1_q_a[2] is sinlup:U_sinlup|romtab:U_romtab|lpm_rom:LPM_ROM_component|altrom:srom|altsyncram:rom_block|altsyncram_86r:auto_generated|q_a[2]
--RAM Block Operation Mode: ROM
--Port A Depth: 64, Port A Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 7
--Port A Input: Registered, Port A Output: Un-registered
Q1_q_a[2]_PORT_A_address = BUS(F1_phaseadd[0], F1_phaseadd[1], F1_phaseadd[2], F1_phaseadd[3], F1_phaseadd[4], F1_phaseadd[5]);
Q1_q_a[2]_PORT_A_address_reg = DFFE(Q1_q_a[2]_PORT_A_address, Q1_q_a[2]_clock_0, , , );
Q1_q_a[2]_clock_0 = SYSCLK;
Q1_q_a[2]_PORT_A_data_out = MEMORY(, , Q1_q_a[2]_PORT_A_address_reg, , , , , , Q1_q_a[2]_clock_0, , , , , );
Q1_q_a[2] = Q1_q_a[2]_PORT_A_data_out[0];


--Q1_q_a[3] is sinlup:U_sinlup|romtab:U_romtab|lpm_rom:LPM_ROM_component|altrom:srom|altsyncram:rom_block|altsyncram_86r:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 64, Port A Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 7
--Port A Input: Registered, Port A Output: Un-registered
Q1_q_a[3]_PORT_A_address = BUS(F1_phaseadd[0], F1_phaseadd[1], F1_phaseadd[2], F1_phaseadd[3], F1_phaseadd[4], F1_phaseadd[5]);
Q1_q_a[3]_PORT_A_address_reg = DFFE(Q1_q_a[3]_PORT_A_address, Q1_q_a[3]_clock_0, , , );
Q1_q_a[3]_clock_0 = SYSCLK;
Q1_q_a[3]_PORT_A_data_out = MEMORY(, , Q1_q_a[3]_PORT_A_address_reg, , , , , , Q1_q_a[3]_clock_0, , , , , );
Q1_q_a[3] = Q1_q_a[3]_PORT_A_data_out[0];


--Q1_q_a[4] is sinlup:U_sinlup|romtab:U_romtab|lpm_rom:LPM_ROM_component|altrom:srom|altsyncram:rom_block|altsyncram_86r:auto_generated|q_a[4]
--RAM Block Operation Mode: ROM
--Port A Depth: 64, Port A Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 7
--Port A Input: Registered, Port A Output: Un-registered
Q1_q_a[4]_PORT_A_address = BUS(F1_phaseadd[0], F1_phaseadd[1], F1_phaseadd[2], F1_phaseadd[3], F1_phaseadd[4], F1_phaseadd[5]);
Q1_q_a[4]_PORT_A_address_reg = DFFE(Q1_q_a[4]_PORT_A_address, Q1_q_a[4]_clock_0, , , );
Q1_q_a[4]_clock_0 = SYSCLK;
Q1_q_a[4]_PORT_A_data_out = MEMORY(, , Q1_q_a[4]_PORT_A_address_reg, , , , , , Q1_q_a[4]_clock_0, , , , , );
Q1_q_a[4] = Q1_q_a[4]_PORT_A_data_out[0];


--Q1_q_a[5] is sinlup:U_sinlup|romtab:U_romtab|lpm_rom:LPM_ROM_component|altrom:srom|altsyncram:rom_block|altsyncram_86r:auto_generated|q_a[5]
--RAM Block Operation Mode: ROM
--Port A Depth: 64, Port A Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 7