📄 romtab.vhd
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-----------------------------------------------------------------------------
-- Project Name : NCO
--
-- Author : Bluetea
-- Creation Date : 03/11/04 18:20:21
-- Version Number : 1.0
-- Description :
-- This ,module is the 1/4 wave sin lookup table. The input to the block is
-- the phase angle value and the output is the 8 bit sin value.
-----------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY romtab IS
PORT(
SYSCLK : IN STD_LOGIC;
PHASEADD : IN STD_LOGIC_VECTOR (5 DOWNTO 0);--phase address value
QWAVESIN : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) --1/4 wave sin value
);
END romtab;
ARCHITECTURE ROM OF romtab IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (6 DOWNTO 0);
COMPONENT LPM_ROM --sine wave ROM
GENERIC (
LPM_WIDTH : POSITIVE;
LPM_WIDTHAD : POSITIVE;
LPM_ADDRESS_CONTROL : STRING;
LPM_INDATA : STRING;
LPM_OUTDATA : STRING;
LPM_FILE : STRING
);
PORT (
address : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
inclock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
);
END COMPONENT;
BEGIN
QWAVESIN <= sub_wire0(6 DOWNTO 0);
LPM_ROM_component : LPM_ROM
GENERIC MAP (
LPM_WIDTH => 7,
LPM_WIDTHAD => 6,
LPM_ADDRESS_CONTROL => "REGISTERED",
LPM_INDATA => "REGISTERED",
LPM_OUTDATA => "UNREGISTERED",
LPM_FILE => "G:\\test\\quartus\\NCO\\ncosin.mif"
)
PORT MAP (
address => PHASEADD,
inclock => SYSCLK,
q => sub_wire0
);
END ROM;
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