nco.fit.eqn

使用QUARTUS 2编译的DDS的源码

C1_load_lut_out = !C1_pwwrns & (C1_pwwrnm);
C1_load = DFFEAS(C1_load_lut_out, GLOBAL(SYSCLK), VCC, , , , , RESETN, );


--C1L10 is loadpw:U_loadpw|phswd[6]~133 at LC_X32_Y22_N7
--operation mode is normal

C1L10 = RESETN # C1_load;


--C1_phswd[5] is loadpw:U_loadpw|phswd[5] at LC_X32_Y22_N6
--operation mode is normal

C1_phswd[5]_lut_out = !RESETN & (PHASEWORD[5]);
C1_phswd[5] = DFFEAS(C1_phswd[5]_lut_out, GLOBAL(SYSCLK), VCC, , C1L10, , , , );


--E1_mphsreg[4] is phasemod:U_phasemod|mphsreg[4] at LC_X31_Y24_N4
--operation mode is arithmetic

E1_mphsreg[4]_lut_out = C1_phswd[4] $ D1_pipe4[4] $ !E1L13;
E1_mphsreg[4] = DFFEAS(E1_mphsreg[4]_lut_out, GLOBAL(SYSCLK), VCC, , , , , RESETN, );

--E1L16 is phasemod:U_phasemod|mphsreg[4]~101 at LC_X31_Y24_N4
--operation mode is arithmetic

E1L16 = E1L17;


--Q1_q_a[0] is sinlup:U_sinlup|romtab:U_romtab|lpm_rom:LPM_ROM_component|altrom:srom|altsyncram:rom_block|altsyncram_86r:auto_generated|q_a[0] at M512_X26_Y24
--RAM Block Operation Mode: ROM
--Port A Depth: 64, Port A Width: 7
--Port A Logical Depth: 64, Port A Logical Width: 7
--Port A Input: Registered, Port A Output: Un-registered
Q1_q_a[0]_PORT_A_address = BUS(F1_phaseadd[0], F1_phaseadd[1], F1_phaseadd[2], F1_phaseadd[3], F1_phaseadd[4], F1_phaseadd[5]);
Q1_q_a[0]_PORT_A_address_reg = DFFE(Q1_q_a[0]_PORT_A_address, Q1_q_a[0]_clock_0, , , );
Q1_q_a[0]_clock_0 = GLOBAL(SYSCLK);
Q1_q_a[0]_PORT_A_data_out = MEMORY(, , Q1_q_a[0]_PORT_A_address_reg, , , , , , Q1_q_a[0]_clock_0, , , , , );
Q1_q_a[0] = Q1_q_a[0]_PORT_A_data_out[0];

--Q1_q_a[6] is sinlup:U_sinlup|romtab:U_romtab|lpm_rom:LPM_ROM_component|altrom:srom|altsyncram:rom_block|altsyncram_86r:auto_generated|q_a[6] at M512_X26_Y24
Q1_q_a[0]_PORT_A_address = BUS(F1_phaseadd[0], F1_phaseadd[1], F1_phaseadd[2], F1_phaseadd[3], F1_phaseadd[4], F1_phaseadd[5]);
Q1_q_a[0]_PORT_A_address_reg = DFFE(Q1_q_a[0]_PORT_A_address, Q1_q_a[0]_clock_0, , , );
Q1_q_a[0]_clock_0 = GLOBAL(SYSCLK);
Q1_q_a[0]_PORT_A_data_out = MEMORY(, , Q1_q_a[0]_PORT_A_address_reg, , , , , , Q1_q_a[0]_clock_0, , , , , );
Q1_q_a[6] = Q1_q_a[0]_PORT_A_data_out[6];

--Q1_q_a[5] is sinlup:U_sinlup|romtab:U_romtab|lpm_rom:LPM_ROM_component|altrom:srom|altsyncram:rom_block|altsyncram_86r:auto_generated|q_a[5] at M512_X26_Y24
Q1_q_a[0]_PORT_A_address = BUS(F1_phaseadd[0], F1_phaseadd[1], F1_phaseadd[2], F1_phaseadd[3], F1_phaseadd[4], F1_phaseadd[5]);
Q1_q_a[0]_PORT_A_address_reg = DFFE(Q1_q_a[0]_PORT_A_address, Q1_q_a[0]_clock_0, , , );
Q1_q_a[0]_clock_0 = GLOBAL(SYSCLK);
Q1_q_a[0]_PORT_A_data_out = MEMORY(, , Q1_q_a[0]_PORT_A_address_reg, , , , , , Q1_q_a[0]_clock_0, , , , , );
Q1_q_a[5] = Q1_q_a[0]_PORT_A_data_out[5];

--Q1_q_a[4] is sinlup:U_sinlup|romtab:U_romtab|lpm_rom:LPM_ROM_component|altrom:srom|altsyncram:rom_block|altsyncram_86r:auto_generated|q_a[4] at M512_X26_Y24
Q1_q_a[0]_PORT_A_address = BUS(F1_phaseadd[0], F1_phaseadd[1], F1_phaseadd[2], F1_phaseadd[3], F1_phaseadd[4], F1_phaseadd[5]);
Q1_q_a[0]_PORT_A_address_reg = DFFE(Q1_q_a[0]_PORT_A_address, Q1_q_a[0]_clock_0, , , );
Q1_q_a[0]_clock_0 = GLOBAL(SYSCLK);
Q1_q_a[0]_PORT_A_data_out = MEMORY(, , Q1_q_a[0]_PORT_A_address_reg, , , , , , Q1_q_a[0]_clock_0, , , , , );
Q1_q_a[4] = Q1_q_a[0]_PORT_A_data_out[4];

--Q1_q_a[3] is sinlup:U_sinlup|romtab:U_romtab|lpm_rom:LPM_ROM_component|altrom:srom|altsyncram:rom_block|altsyncram_86r:auto_generated|q_a[3] at M512_X26_Y24
Q1_q_a[0]_PORT_A_address = BUS(F1_phaseadd[0], F1_phaseadd[1], F1_phaseadd[2], F1_phaseadd[3], F1_phaseadd[4], F1_phaseadd[5]);
Q1_q_a[0]_PORT_A_address_reg = DFFE(Q1_q_a[0]_PORT_A_address, Q1_q_a[0]_clock_0, , , );
Q1_q_a[0]_clock_0 = GLOBAL(SYSCLK);
Q1_q_a[0]_PORT_A_data_out = MEMORY(, , Q1_q_a[0]_PORT_A_address_reg, , , , , , Q1_q_a[0]_clock_0, , , , , );
Q1_q_a[3] = Q1_q_a[0]_PORT_A_data_out[3];

--Q1_q_a[2] is sinlup:U_sinlup|romtab:U_romtab|lpm_rom:LPM_ROM_component|altrom:srom|altsyncram:rom_block|altsyncram_86r:auto_generated|q_a[2] at M512_X26_Y24
Q1_q_a[0]_PORT_A_address = BUS(F1_phaseadd[0], F1_phaseadd[1], F1_phaseadd[2], F1_phaseadd[3], F1_phaseadd[4], F1_phaseadd[5]);
Q1_q_a[0]_PORT_A_address_reg = DFFE(Q1_q_a[0]_PORT_A_address, Q1_q_a[0]_clock_0, , , );
Q1_q_a[0]_clock_0 = GLOBAL(SYSCLK);
Q1_q_a[0]_PORT_A_data_out = MEMORY(, , Q1_q_a[0]_PORT_A_address_reg, , , , , , Q1_q_a[0]_clock_0, , , , , );
Q1_q_a[2] = Q1_q_a[0]_PORT_A_data_out[2];

--Q1_q_a[1] is sinlup:U_sinlup|romtab:U_romtab|lpm_rom:LPM_ROM_component|altrom:srom|altsyncram:rom_block|altsyncram_86r:auto_generated|q_a[1] at M512_X26_Y24
Q1_q_a[0]_PORT_A_address = BUS(F1_phaseadd[0], F1_phaseadd[1], F1_phaseadd[2], F1_phaseadd[3], F1_phaseadd[4], F1_phaseadd[5]);
Q1_q_a[0]_PORT_A_address_reg = DFFE(Q1_q_a[0]_PORT_A_address, Q1_q_a[0]_clock_0, , , );
Q1_q_a[0]_clock_0 = GLOBAL(SYSCLK);
Q1_q_a[0]_PORT_A_data_out = MEMORY(, , Q1_q_a[0]_PORT_A_address_reg, , , , , , Q1_q_a[0]_clock_0, , , , , );
Q1_q_a[1] = Q1_q_a[0]_PORT_A_data_out[1];


--F1L19 is sinlup:U_sinlup|add~138 at LC_X30_Y24_N1
--operation mode is arithmetic

F1L19_cout_0 = !F1_qwavesin_ff[0];
F1L19 = CARRY(F1L19_cout_0);

--F1L20 is sinlup:U_sinlup|add~138COUT1_142 at LC_X30_Y24_N1
--operation mode is arithmetic

F1L20_cout_1 = !F1_qwavesin_ff[0];
F1L20 = CARRY(F1L20_cout_1);


--F1_modphase_msb2_ff is sinlup:U_sinlup|modphase_msb2_ff at LC_X29_Y24_N8
--operation mode is normal

F1_modphase_msb2_ff_lut_out = !RESETN & (F1_modphase_msb1_ff);
F1_modphase_msb2_ff = DFFEAS(F1_modphase_msb2_ff_lut_out, GLOBAL(SYSCLK), VCC, , , , , , );


--B1_loadp3 is loadfw:U_loadfw|loadp3 at LC_X35_Y22_N0
--operation mode is normal

B1_loadp3_lut_out = !RESETN & (B1_loadp2);
B1_loadp3 = DFFEAS(B1_loadp3_lut_out, GLOBAL(SYSCLK), VCC, , , , , , );


--B1_pipefw4[4] is loadfw:U_loadfw|pipefw4[4] at LC_X33_Y24_N7
--operation mode is normal

B1_pipefw4[4]_lut_out = !RESETN & (FREQWORD[28]);
B1_pipefw4[4] = DFFEAS(B1_pipefw4[4]_lut_out, GLOBAL(SYSCLK), VCC, , B1L41, , , , );


--D1_pipe4[3] is phasea:U_phasea|pipe4[3] at LC_X32_Y24_N4
--operation mode is arithmetic

D1_pipe4[3]_lut_out = D1_pipe4[3] $ B1_pipefw4[3] $ !D1L40;
D1_pipe4[3] = DFFEAS(D1_pipe4[3]_lut_out, GLOBAL(SYSCLK), VCC, , , , , RESETN, );

--D1L43 is phasea:U_phasea|pipe4[3]~111 at LC_X32_Y24_N4
--operation mode is arithmetic

D1L43 = D1L44;


--C1_pwwrns is loadpw:U_loadpw|pwwrns at LC_X31_Y22_N2
--operation mode is normal

C1_pwwrns_lut_out = RESETN # C1_pwwrnm;
C1_pwwrns = DFFEAS(C1_pwwrns_lut_out, GLOBAL(SYSCLK), VCC, , , , , , );


--C1_pwwrnm is loadpw:U_loadpw|pwwrnm at LC_X31_Y22_N4
--operation mode is normal

C1_pwwrnm_lut_out = RESETN # PWWRN;
C1_pwwrnm = DFFEAS(C1_pwwrnm_lut_out, GLOBAL(SYSCLK), VCC, , , , , , );


--C1_phswd[4] is loadpw:U_loadpw|phswd[4] at LC_X32_Y22_N1
--operation mode is normal

C1_phswd[4]_lut_out = !RESETN & (PHASEWORD[4]);
C1_phswd[4] = DFFEAS(C1_phswd[4]_lut_out, GLOBAL(SYSCLK), VCC, , C1L10, , , , );


--E1_mphsreg[3] is phasemod:U_phasemod|mphsreg[3] at LC_X31_Y24_N3
--operation mode is arithmetic

E1_mphsreg[3]_lut_out = D1_pipe4[3] $ C1_phswd[3] $ E1L10;
E1_mphsreg[3] = DFFEAS(E1_mphsreg[3]_lut_out, GLOBAL(SYSCLK), VCC, , , , , RESETN, );

--E1L13 is phasemod:U_phasemod|mphsreg[3]~105 at LC_X31_Y24_N3
--operation mode is arithmetic

E1L13_cout_0 = D1_pipe4[3] & !C1_phswd[3] & !E1L10 # !D1_pipe4[3] & (!E1L10 # !C1_phswd[3]);
E1L13 = CARRY(E1L13_cout_0);

--E1L14 is phasemod:U_phasemod|mphsreg[3]~105COUT1 at LC_X31_Y24_N3
--operation mode is arithmetic

E1L14_cout_1 = D1_pipe4[3] & !C1_phswd[3] & !E1L11 # !D1_pipe4[3] & (!E1L11 # !C1_phswd[3]);
E1L14 = CARRY(E1L14_cout_1);


--F1_phaseadd[0] is sinlup:U_sinlup|phaseadd[0] at LC_X31_Y22_N5
--operation mode is normal

F1_phaseadd[0]_lut_out = E1_mphsreg[6] $ E1_mphsreg[0];
F1_phaseadd[0] = DFFEAS(F1_phaseadd[0]_lut_out, GLOBAL(SYSCLK), VCC, , , , , RESETN, );


--F1_phaseadd[1] is sinlup:U_sinlup|phaseadd[1] at LC_X31_Y22_N8
--operation mode is normal

F1_phaseadd[1]_lut_out = E1_mphsreg[1] $ (E1_mphsreg[6]);
F1_phaseadd[1] = DFFEAS(F1_phaseadd[1]_lut_out, GLOBAL(SYSCLK), VCC, , , , , RESETN, );


--F1_phaseadd[2] is sinlup:U_sinlup|phaseadd[2] at LC_X31_Y22_N3
--operation mode is normal

F1_phaseadd[2]_lut_out = E1_mphsreg[6] $ E1_mphsreg[2];
F1_phaseadd[2] = DFFEAS(F1_phaseadd[2]_lut_out, GLOBAL(SYSCLK), VCC, , , , , RESETN, );


--F1_phaseadd[3] is sinlup:U_sinlup|phaseadd[3] at LC_X31_Y22_N7
--operation mode is normal

F1_phaseadd[3]_lut_out = E1_mphsreg[6] $ E1_mphsreg[3];
F1_phaseadd[3] = DFFEAS(F1_phaseadd[3]_lut_out, GLOBAL(SYSCLK), VCC, , , , , RESETN, );


--F1_phaseadd[4] is sinlup:U_sinlup|phaseadd[4] at LC_X31_Y22_N9
--operation mode is normal

F1_phaseadd[4]_lut_out = E1_mphsreg[4] $ E1_mphsreg[6];
F1_phaseadd[4] = DFFEAS(F1_phaseadd[4]_lut_out, GLOBAL(SYSCLK), VCC, , , , , RESETN, );


--F1_phaseadd[5] is sinlup:U_sinlup|phaseadd[5] at LC_X31_Y22_N1
--operation mode is normal

F1_phaseadd[5]_lut_out = E1_mphsreg[5] $ E1_mphsreg[6];
F1_phaseadd[5] = DFFEAS(F1_phaseadd[5]_lut_out, GLOBAL(SYSCLK), VCC, , , , , RESETN, );


--F1_modphase_msb1_ff is sinlup:U_sinlup|modphase_msb1_ff at LC_X29_Y24_N0
--operation mode is normal

F1_modphase_msb1_ff_lut_out = !RESETN & (E1_mphsreg[7]);
F1_modphase_msb1_ff = DFFEAS(F1_modphase_msb1_ff_lut_out, GLOBAL(SYSCLK), VCC, , , , , , );


--B1_loadp2 is loadfw:U_loadfw|loadp2 at LC_X31_Y25_N9
--operation mode is normal

B1_loadp2_lut_out = B1_loadp1 & !RESETN;
B1_loadp2 = DFFEAS(B1_loadp2_lut_out, GLOBAL(SYSCLK), VCC, , , , , , );


--B1_pipefw4[3] is loadfw:U_loadfw|pipefw4[3] at LC_X33_Y24_N6
--operation mode is normal

B1_pipefw4[3]_lut_out = !RESETN & FREQWORD[27];
B1_pipefw4[3] = DFFEAS(B1_pipefw4[3]_lut_out, GLOBAL(SYSCLK), VCC, , B1L41, , , , );


--D1_pipe4[2] is phasea:U_phasea|pipe4[2] at LC_X32_Y24_N3
--operation mode is arithmetic

D1_pipe4[2]_lut_out = D1_pipe4[2] $ B1_pipefw4[2] $ D1L37;
D1_pipe4[2] = DFFEAS(D1_pipe4[2]_lut_out, GLOBAL(SYSCLK), VCC, , , , , RESETN, );

--D1L40 is phasea:U_phasea|pipe4[2]~115 at LC_X32_Y24_N3
--operation mode is arithmetic

D1L40_cout_0 = D1_pipe4[2] & !B1_pipefw4[2] & !D1L37 # !D1_pipe4[2] & (!D1L37 # !B1_pipefw4[2]);
D1L40 = CARRY(D1L40_cout_0);

--D1L41 is phasea:U_phasea|pipe4[2]~115COUT1 at LC_X32_Y24_N3
--operation mode is arithmetic

D1L41_cout_1 = D1_pipe4[2] & !B1_pipefw4[2] & !D1L38 # !D1_pipe4[2] & (!D1L38 # !B1_pipefw4[2]);
D1L41 = CARRY(D1L41_cout_1);


--C1_phswd[3] is loadpw:U_loadpw|phswd[3] at LC_X32_Y22_N9
--operation mode is normal

C1_phswd[3]_lut_out = !RESETN & (PHASEWORD[3]);
C1_phswd[3] = DFFEAS(C1_phswd[3]_lut_out, GLOBAL(SYSCLK), VCC, , C1L10, , , , );


--E1_mphsreg[2] is phasemod:U_phasemod|mphsreg[2] at LC_X31_Y24_N2
--operation mode is arithmetic

E1_mphsreg[2]_lut_out = C1_phswd[2] $ D1_pipe4[2] $ !E1L7;
E1_mphsreg[2] = DFFEAS(E1_mphsreg[2]_lut_out, GLOBAL(SYSCLK), VCC, , , , , RESETN, );

--E1L10 is phasemod:U_phasemod|mphsreg[2]~109 at LC_X31_Y24_N2
--operation mode is arithmetic

E1L10_cout_0 = C1_phswd[2] & (D1_pipe4[2] # !E1L7) # !C1_phswd[2] & D1_pipe4[2] & !E1L7;
E1L10 = CARRY(E1L10_cout_0);

--E1L11 is phasemod:U_phasemod|mphsreg[2]~109COUT1_123 at LC_X31_Y24_N2
--operation mode is arithmetic

E1L11_cout_1 = C1_phswd[2] & (D1_pipe4[2] # !E1L8) # !C1_phswd[2] & D1_pipe4[2] & !E1L8;
E1L11 = CARRY(E1L11_cout_1);


--E1_mphsreg[0] is phasemod:U_phasemod|mphsreg[0] at LC_X31_Y24_N0
--operation mode is arithmetic

E1_mphsreg[0]_lut_out = D1_pipe4[0] $ C1_phswd[0];
E1_mphsreg[0] = DFFEAS(E1_mphsreg[0]_lut_out, GLOBAL(SYSCLK), VCC, , , , , RESETN, );

--E1L4 is phasemod:U_phasemod|mphsreg[0]~113 at LC_X31_Y24_N0
--operation mode is arithmetic

E1L4_cout_0 = D1_pipe4[0] & C1_phswd[0];
E1L4 = CARRY(E1L4_cout_0);

--E1L5 is phasemod:U_phasemod|mphsreg[0]~113COUT1_121 at LC_X31_Y24_N0
--operation mode is arithmetic

E1L5_cout_1 = D1_pipe4[0] & C1_phswd[0];
E1L5 = CARRY(E1L5_cout_1);


--E1_mphsreg[1] is phasemod:U_phasemod|mphsreg[1] at LC_X31_Y24_N1
--operation mode is arithmetic

E1_mphsreg[1]_lut_out = C1_phswd[1] $ D1_pipe4[1] $ E1L4;
E1_mphsreg[1] = DFFEAS(E1_mphsreg[1]_lut_out, GLOBAL(SYSCLK), VCC, , , , , RESETN, );

--E1L7 is phasemod:U_phasemod|mphsreg[1]~117 at LC_X31_Y24_N1
--operation mode is arithmetic

E1L7_cout_0 = C1_phswd[1] & !D1_pipe4[1] & !E1L4 # !C1_phswd[1] & (!E1L4 # !D1_pipe4[1]);
E1L7 = CARRY(E1L7_cout_0);

--E1L8 is phasemod:U_phasemod|mphsreg[1]~117COUT1_122 at LC_X31_Y24_N1
--operation mode is arithmetic

E1L8_cout_1 = C1_phswd[1] & !D1_pipe4[1] & !E1L5 # !C1_phswd[1] & (!E1L5 # !D1_pipe4[1]);
E1L8 = CARRY(E1L8_cout_1);


--B1_loadp1 is loadfw:U_loadfw|loadp1 at LC_X36_Y21_N0
--operation mode is normal

B1_loadp1_lut_out = !B1_fwwrns & (B1_fwwrnm);
B1_loadp1 = DFFEAS(B1_loadp1_lut_out, GLOBAL(SYSCLK), VCC, , , , , RESETN, );


--B1_pipefw4[2] is loadfw:U_loadfw|pipefw4[2] at LC_X33_Y24_N8
--operation mode is normal

B1_pipefw4[2]_lut_out = !RESETN & (FREQWORD[26]);
B1_pipefw4[2] = DFFEAS(B1_pipefw4[2]_lut_out, GLOBAL(SYSCLK), VCC, , B1L41, , , , );


--D1_pipe4[1] is phasea:U_phasea|pipe4[1] at LC_X32_Y24_N2
--operation mode is arithmetic

D1_pipe4[1]_lut_out = D1_pipe4[1] $ B1_pipefw4[1] $ !D1L31;
D1_pipe4[1] = DFFEAS(D1_pipe4[1]_lut_out, GLOBAL(SYSCLK), VCC, , , , , RESETN, );

--D1L37 is phasea:U_phasea|pipe4[1]~119 at LC_X32_Y24_N2
--operation mode is arithmetic

D1L37_cout_0 = D1_pipe4[1] & (B1_pipefw4[1] # !D1L31) # !D1_pipe4[1] & B1_pipefw4[1] & !D1L31;
D1L37 = CARRY(D1L37_cout_0);

--D1L38 is phasea:U_phasea|pipe4[1]~119COUT1_136 at LC_X32_Y24_N2
--operation mode is arithmetic

D1L38_cout_1 = D1_pipe4[1] & (B1_pipefw4[1] # !D1L32) # !D1_pipe4[1] & B1_pipefw4[1] & !D1L32;
D1L38 = CARRY(D1L38_cout_1);


--C1_phswd[2] is loadpw:U_loadpw|phswd[2] at LC_X32_Y22_N3
--operation mode is normal

C1_phswd[2]_lut_out = !RESETN & (PHASEWORD[2]);
C1_phswd[2] = DFFEAS(C1_phswd[2]_lut_out, GLOBAL(SYSCLK), VCC, , C1L10, , , , );


--D1_pipe4[0] is phasea:U_phasea|pipe4[0] at LC_X32_Y24_N1
--operation mode is arithmetic

D1_pipe4[0]_lut_out = B1_pipefw4[0] $ D1_pipe4[0] $ D1L34;
D1_pipe4[0] = DFFEAS(D1_pipe4[0]_lut_out, GLOBAL(SYSCLK), VCC, , , , , RESETN, );

--D1L31 is phasea:U_phasea|pipe4[0]~123 at LC_X32_Y24_N1
--operation mode is arithmetic

D1L31_cout_0 = B1_pipefw4[0] & !D1_pipe4[0] & !D1L34 # !B1_pipefw4[0] & (!D1L34 # !D1_pipe4[0]);
D1L31 = CARRY(D1L31_cout_0);

--D1L32 is phasea:U_phasea|pipe4[0]~123COUT1_135 at LC_X32_Y24_N1
--operation mode is arithmetic

D1L32_cout_1 = B1_pipefw4[0] & !D1_pipe4[0] & !D1L35 # !B1_pipefw4[0] & (!D1L35 # !D1_pipe4[0]);
D1L32 = CARRY(D1L32_cout_1);


--C1_phswd[0] is loadpw:U_loadpw|phswd[0] at LC_X32_Y22_N4
--operation mode is normal

C1_phswd[0]_lut_out = !RESETN & (PHASEWORD[0]);
C1_phswd[0] = DFFEAS(C1_phswd[0]_lut_out, GLOBAL(SYSCLK), VCC, , C1L10, , , , );


--C1_phswd[1] is loadpw:U_loadpw|phswd[1] at LC_X33_Y22_N8
--operation mode is normal

C1_phswd[1]_lut_out = !RESETN & (PHASEWORD[1]);
C1_phswd[1] = DFFEAS(C1_phswd[1]_lut_out, GLOBAL(SYSCLK), VCC, , C1L10, , , , );


--B1_fwwrns is loadfw:U_loadfw|fwwrns at LC_X33_Y22_N5
--operation mode is normal

B1_fwwrns_lut_out = RESETN # B1_fwwrnm;
B1_fwwrns = DFFEAS(B1_fwwrns_lut_out, GLOBAL(SYSCLK), VCC, , , , , , );


--B1_fwwrnm is loadfw:U_loadfw|fwwrnm at LC_X33_Y22_N9