allegro.jrl

ACTEL A3P StartKit FPGA开发全套文挡（含测试源码）

\t (00:00:07) allegro 15.51 p006 (v15-5.1-43E) i86
\t (00:00:07) 

\t (00:00:11) Starting new drawing...
\t (00:00:12) Grids are drawn 400.0, 400.0 apart for enhanced viewability.
\i (00:00:12) trapsize 823
\i (00:00:12) trapsize 986
\i (00:00:14) trapsize 986
\i (00:00:19) open 
\i (00:00:44) fillin "E:\EDA\范例\FusionStarterKit_Board_DesignFiles\FusionStarterKit_Board_DesignFiles\s1715_fusion_012606.brd"
\i (00:00:44) cd "E:\EDA\范例\FusionStarterKit_Board_DesignFiles\FusionStarterKit_Board_DesignFiles"
\t (00:00:44) Opening existing drawing...
\w (00:00:44) Allegro PCB opening an Allegro Expert design.
\w (00:00:44) DRC set to "out of date", this product supports a different DRC set then last product used on drawing.
\w (00:00:44) Database was last saved by a higher tier tool, Allegro Expert. There may be constraints, rules and other design data that may be ignored in this tool.
\i (00:00:54) fillin confirm
\t (00:00:54) Grids are drawn 320.0000, 320.0000 apart for enhanced viewability.
\i (00:00:54) trapsize 1056601
\d (00:00:55) Database opened: E:/EDA/范例/FusionStarterKit_Board_DesignFiles/FusionStarterKit_Board_DesignFiles/s1715_fusion_012606.brd
\i (00:01:12) zoom previous 
\i (00:01:12) trapsize 1056601
\i (00:01:12) zoom previous 
\i (00:01:12) trapsize 1056601
\i (00:01:20) setwindow form.mini
\i (00:01:20) FORM mini subclass ASSEMBLY_BOTTOM 
\i (00:01:36) FORM mini subclass DESIGN_NOTES 
\i (00:01:39) FORM mini subclass DFA_BOUND_BOTTOM 
\i (00:01:41) FORM mini subclass DIMENSION 
\i (00:02:09) setwindow pcb
\i (00:02:09) zoom previous 
\i (00:02:09) trapsize 1056601
\i (00:02:12) zoom in 
\i (00:02:12) setwindow pcb
\i (00:02:12) zoom in 6792.8568 2989.7750
\t (00:02:12) Grids are drawn 80.0000, 80.0000 apart for enhanced viewability.
\i (00:02:12) trapsize 528300
\i (00:02:15) zoom in 
\i (00:02:15) setwindow pcb
\i (00:02:15) zoom in 6792.8568 2989.7750
\i (00:02:15) trapsize 264150
\i (00:02:21) setwindow form.mini
\i (00:02:21) FORM mini class ANTI ETCH 
\i (00:02:23) FORM mini subclass GND2 
\i (00:02:25) FORM mini subclass SIG3 
\i (00:02:27) FORM mini subclass SIG4 
\i (00:02:30) FORM mini subcolor 1 
\i (00:02:30) FORM mini subcolor 0 
\i (00:02:31) FORM mini subcolor 1 
\i (00:02:32) FORM mini subcolor 0 
\i (00:02:35) FORM mini subclass SIG3 
\i (00:02:38) FORM mini subclass BOTTOM 
\i (00:02:40) FORM mini subcolor 1 
\i (00:02:41) FORM mini subcolor 0 
\i (00:02:41) FORM mini subcolor 1 
\i (00:02:42) FORM mini subcolor 0 
\i (00:02:44) FORM mini class BOARD GEOMETRY 
\i (00:02:46) FORM mini subcolor 1 
\i (00:02:46) FORM mini subcolor 0 
\i (00:02:49) FORM mini class BOUNDARY 
\i (00:02:50) FORM mini subcolor 1 
\i (00:02:51) FORM mini subcolor 0 
\i (00:02:51) FORM mini subcolor 1 
\i (00:02:53) FORM mini subcolor 0 
\i (00:02:57) FORM mini class COMPONENT VALUE 
\i (00:02:58) FORM mini subcolor 1 
\i (00:02:58) FORM mini subcolor 0 
\i (00:02:59) FORM mini subcolor 1 
\i (00:03:04) FORM mini class DEVICE TYPE 
\i (00:03:05) FORM mini subcolor 1 
\i (00:03:05) FORM mini subcolor 0 
\i (00:03:06) FORM mini subcolor 1 
\i (00:03:22) FORM mini class ROUTE KEEPIN 
\i (00:03:24) FORM mini subcolor 1 
\i (00:03:25) FORM mini subcolor 0 
\i (00:03:25) FORM mini subcolor 1 
\i (00:03:26) FORM mini subcolor 0 
\i (00:03:31) FORM mini class VIA CLASS 
\i (00:03:32) FORM mini subcolor 1 
\i (00:03:32) FORM mini subcolor 0 
\i (00:03:43) FORM mini class ROUTE KEEPIN 
\i (00:03:49) setwindow pcb
\i (00:03:49) exit