top_a3pe600.stp

ACTEL A3P StartKit FPGA开发全套文挡（含测试源码）

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INTEGER CHECKSUM=15172;
BOOLEAN UROW[128];
' bit 24-17 and 5-0 unsed
BOOLEAN UROW_MASK[128] = $FFFFFFFFFFFFFFFFFFFFFFFFFE01FFC0;
ENDDATA;

PROCEDURE DO_EXIT USES GV;
IRSTOP IDLE;
IRSCAN 8,$81;
IRSTOP IRPAUSE;
WAIT 20 USEC;
STATE RESET;
EXIT STATUS;
ENDPROC;

PROCEDURE PROC_INIT_AES USES GV;
    IRSCAN 8, $DD;
    DRSTOP IDLE;
    DRSCAN 128, $00000000000000000000000000000000;
    DRSTOP DRPAUSE;
    WAIT 3 CYCLES; 
    WAIT 48 USEC;

ENDPROC;

PROCEDURE PROC_VERIFY_IDCODE USES GV, PROC_INIT_AES, DO_EXIT;
' Shift IDCODE instruction
IRSCAN 8,$0F;
DRSCAN 32, $00000000, CAPTURE ID[], COMPARE $123261CF,$0EFFFFFF,PASS;
IF PASS ==1 THEN GOTO idok;
STATUS = 6;
PRINT "Failed to verify IDCODE";

EXIT STATUS;

idok:

    CALL PROC_INIT_AES;
    IRSCAN 8, $0A;
    DRSTOP IDLE;
    DRSCAN 128, $E137623A2EEEE91126015F3F73664945;
    DRSTOP DRPAUSE;
    WAIT 3 CYCLES;
    WAIT 256 USEC;

    DRSCAN 128, $00000000000000000000000000000000, CAPTURE Buff128[];

    IF Buff128[127] THEN GOTO M7VerDone;

    STATUS = -31;
    PRINT "Failed to verify AES Sec.";
    CALL DO_EXIT;
    M7VerDone:
    
    IF 1 THEN GOTO RegDev;

    IF Buff128[126] THEN GOTO M7idok;
    STATUS = -32;
    PRINT "Failed to verify IDCODE.";
    PRINT "The Target is not an M7 Device.";
    CALL DO_EXIT;
    
    RegDev:

    IF Buff128[126]==0 THEN GOTO M7idok;
    STATUS = -32;
    PRINT "Failed to verify IDCODE.";
    PRINT "M7 Device detected.";
    CALL DO_EXIT;
    
    M7idok:

IDRev =INT(ID[31..28]);
ENDPROC;

PROCEDURE DO_VERIFY_IDCODE USES PROC_VERIFY_IDCODE;
WAIT RESET, 5 CYCLES;
CALL PROC_VERIFY_IDCODE;
ENDPROC;

PROCEDURE PROC_BP_VER USES GV;
BOOLEAN PLAYER_VERSION_BOOLEAN[32];
PLAYER_VERSION_BOOLEAN[31..0] = BOOL(PLAYER_VERSION_VARIABLE);

INTEGER PLAYER_MAJOR_VERSION = INT (PLAYER_VERSION_BOOLEAN[23..16]) - SCULPTOR_MAJOR_BASE;
INTEGER PLAYER_MINOR_VERSION = INT (PLAYER_VERSION_BOOLEAN[15..8]) - SCULPTOR_MINOR_BASE;

ACT_UROW_SW_VERSION[6..5] = BOOL(PLAYER_MAJOR_VERSION);
ACT_UROW_SW_VERSION[4..1] = BOOL(PLAYER_MINOR_VERSION);
ACT_UROW_SW_VERSION[0] = PLAYER_VERSION_BOOLEAN[0];

ENDPROC;

PROCEDURE DO_READ_SECURITY USES GV;
IRSTOP IDLE;
IRSCAN 8,$A4;
IRSTOP IRPAUSE;
WAIT 3 CYCLES;
DRSCAN 44, $00000000000,capture SecReg[];

ULUWE = SecReg[9];
ULARE = SecReg[8];
ULUPC = SecReg[7];
ULUFE = SecReg[6];
ULUFP = SecReg[5];
ULUFJ = SecReg[4];
ULFLR = SecReg[3];
ULULR = SecReg[2];
ULAWE = SecReg[1];
ULARD = SecReg[0];
ULOPT[1] = SecReg[11];
ULOPT[0] = SecReg[10];
ENDPROC;

PROCEDURE DO_CHECK_R USES DO_READ_SECURITY, GV, DO_EXIT;
CALL DO_READ_SECURITY;
IF SECKEY_CHK THEN GOTO SkipRChk;
IF ULARD THEN GOTO ArrayRP;
IF ULARE THEN GOTO ArrayEPR;
GOTO SkipRChk;

ArrayRP:
STATUS = -30;
PRINT "FPGA Array Verification is protected by pass key.";
PRINT "A valid pass key needs to be provided.";
CALL DO_EXIT;

ArrayEPR:
STATUS = -33;
PRINT "FPGA Array Encryption is enforced. Plain text verification is prohibited.";
CALL DO_EXIT;

SkipRChk:
ENDPROC;

PROCEDURE DO_CHECK_W USES DO_READ_SECURITY, GV, DO_CHECK_R, DO_EXIT;
IF SECKEY_CHK THEN GOTO SkipWChk;
CALL DO_READ_SECURITY;
IF ULAWE THEN GOTO ArrayWP;
IF ULARD THEN GOTO ArrayRPW;
IF ULARE THEN GOTO ArrayEPW;
CALL DO_CHECK_R;

GOTO SkipWChk;

ArrayWP:
STATUS = -28;
PRINT "FPGA Array Write/Erase is protected by pass key.";
PRINT "A valid pass key needs to be provided.";
CALL DO_EXIT;

ArrayRPW:
STATUS = -30;
PRINT "FPGA Array Verification is protected by pass key.";
PRINT "A valid pass key needs to be provided.";
CALL DO_EXIT;

ArrayEPW:
STATUS = -33;
PRINT "FPGA Array Encryption is enforced. Plain text programming is prohibited.";
CALL DO_EXIT;

ArrayEPW_B:
STATUS = -37;
PRINT "FPGA Array Encryption is not enforced.";
PRINT "Cannot gaurantee valid AES key present in target device.";
PRINT "Unable to proceed with Encrypted FPGA Array programming.";
CALL DO_EXIT;

SkipWChk:
ENDPROC;