test_tbench.vhd

ACTEL A3P StartKit FPGA开发全套文挡（含测试源码）

-- Generated by WaveFormer Lite Version 10.04a at 10:44:50 on 8/2/2005
-- Stimulator for stimulus

-- Generation Settings:
--   Export type: Stimulus only (reactive export not enabled)

-- Clock Domains:

--   Unclocked
--   ---------
--     Signals:
--       HexA
--       HexB
--       SW1
--       SW2
--       SW4
--       SW3
--       SW6

library ieee, std;
use ieee.std_logic_1164.all;
library syncad_vhdl_lib;
use syncad_vhdl_lib.TBDefinitions.all;
-- Additional libraries used by Model Under Test.
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.NUMERIC_BIT.all;
use ieee.STD_LOGIC_ARITH.all;
-- End Additional libraries used by Model Under Test.

entity stimulus is
  port (
    DATA_LCD : in std_logic_vector(7 downto 4) := "ZZZZ";
    LED : in std_logic_vector(7 downto 0) := "ZZZZZZZZ";
    HexA : inout std_logic_vector(3 downto 0) := x"1";
    HexB : inout std_logic_vector(3 downto 0) := x"1";
    CLK : inout std_logic := '0';
    SW1 : inout std_logic := '0';
    SW5 : inout std_logic := '0';
    RS_LCD : in std_logic := 'Z';
    EN_LCD : in std_logic := 'Z';
    R_nW_LCD : in std_logic := 'Z';
    SW2 : inout std_logic := '0';
    SW4 : inout std_logic := '0';
    SW3 : inout std_logic := '1';
    SW6 : inout std_logic := '0');

end stimulus;

architecture STIMULATOR of stimulus is

  -- Control Signal Declarations
  signal tb_status : TStatus;
  signal tb_ParameterInitFlag : boolean := false;

  -- Parm Declarations
  signal SW5_MinHL : time := 0 ns;
  signal SW5_MaxHL : time := 0 ns;
  signal SW5_MinLH : time := 0 ns;
  signal SW5_MaxLH : time := 0 ns;
  signal SW5_JFall : time := 0 ns;
  signal SW5_JRise : time := 0 ns;
  signal SW5_Duty : real := 0.0;
  signal SW5_Period : time := 0 ns;
  signal SW5_Offset : time := 0 ns;
  signal CLK_MinHL : time := 0 ns;
  signal CLK_MaxHL : time := 0 ns;
  signal CLK_MinLH : time := 0 ns;
  signal CLK_MaxLH : time := 0 ns;
  signal CLK_JFall : time := 0 ns;
  signal CLK_JRise : time := 0 ns;
  signal CLK_Duty : real := 0.0;
  signal CLK_Period : time := 0 ns;
  signal CLK_Offset : time := 0 ns;

  -- Status Control block.

begin

  process
    variable good : boolean;
  begin
    wait until tb_ParameterInitFlag;
    tb_status <= TB_ONCE;
    wait for 7004 ns;
    tb_status <= TB_DONE;
    wait;
  end process;

  -- Parm Assignment Block
  AssignParms : process
    variable SW5_MinHL_real : real;
    variable SW5_MaxHL_real : real;
    variable SW5_MinLH_real : real;
    variable SW5_MaxLH_real : real;
    variable SW5_JFall_real : real;
    variable SW5_JRise_real : real;
    variable SW5_Duty_real : real;
    variable SW5_Period_real : real;
    variable SW5_Offset_real : real;
    variable CLK_MinHL_real : real;
    variable CLK_MaxHL_real : real;
    variable CLK_MinLH_real : real;
    variable CLK_MaxLH_real : real;
    variable CLK_JFall_real : real;
    variable CLK_JRise_real : real;
    variable CLK_Duty_real : real;
    variable CLK_Period_real : real;
    variable CLK_Offset_real : real;
  begin
    SW5_MinHL_real := 0.0;
    SW5_MinHL <= SW5_MinHL_real * 1 ns;
    SW5_MaxHL_real := 0.0;
    SW5_MaxHL <= SW5_MaxHL_real * 1 ns;
    SW5_MinLH_real := 0.0;
    SW5_MinLH <= SW5_MinLH_real * 1 ns;
    SW5_MaxLH_real := 0.0;
    SW5_MaxLH <= SW5_MaxLH_real * 1 ns;
    SW5_JFall_real := 0.0;
    SW5_JFall <= SW5_JFall_real * 1 ns;
    SW5_JRise_real := 0.0;
    SW5_JRise <= SW5_JRise_real * 1 ns;
    SW5_Duty_real := 50.0;
    SW5_Duty <= SW5_Duty_real;
    SW5_Period_real := 25.0;
    SW5_Period <= SW5_Period_real * 1 ns;
    SW5_Offset_real := 0.0;
    SW5_Offset <= SW5_Offset_real * 1 ns;
    CLK_MinHL_real := 0.0;
    CLK_MinHL <= CLK_MinHL_real * 1 ns;
    CLK_MaxHL_real := 0.0;
    CLK_MaxHL <= CLK_MaxHL_real * 1 ns;
    CLK_MinLH_real := 0.0;
    CLK_MinLH <= CLK_MinLH_real * 1 ns;
    CLK_MaxLH_real := 0.0;
    CLK_MaxLH <= CLK_MaxLH_real * 1 ns;
    CLK_JFall_real := 0.0;
    CLK_JFall <= CLK_JFall_real * 1 ns;
    CLK_JRise_real := 0.0;
    CLK_JRise <= CLK_JRise_real * 1 ns;
    CLK_Duty_real := 50.0;
    CLK_Duty <= CLK_Duty_real;
    CLK_Period_real := 25.0;
    CLK_Period <= CLK_Period_real * 1 ns;
    CLK_Offset_real := 0.0;
    CLK_Offset <= CLK_Offset_real * 1 ns;
    tb_ParameterInitFlag <= true;
    wait;
  end process;

  -- Clocks

  -- Clock Instantiation
  tb_CLK : entity syncad_vhdl_lib.tb_clock_minmax
    generic map (name => "tb_CLK",
                initialize => true,
                state1 => '1',
                state2 => '0')
    port map (tb_status,
              CLK,
              CLK_MinLH,
              CLK_MaxLH,
              CLK_MinHL,
              CLK_MaxHL,
              CLK_Offset,
              CLK_Period,
              CLK_Duty,
              CLK_JRise,
              CLK_JFall);

  -- Clock Instantiation
  tb_SW5 : entity syncad_vhdl_lib.tb_clock_minmax
    generic map (name => "tb_SW5",
                initialize => true,
                state1 => '1',
                state2 => '0')
    port map (tb_status,
              SW5,
              SW5_MinLH,
              SW5_MaxLH,
              SW5_MinHL,
              SW5_MaxHL,
              SW5_Offset,
              SW5_Period,
              SW5_Duty,
              SW5_JRise,
              SW5_JFall);

  -- Clocked Sequences

  -- Sequence: Unclocked
  Unclocked : process
  begin
    wait for 41 ns;
    SW1 <= '1';
    wait for 57 ns;
    SW1 <= '0';
    wait for 90 ns;
    SW4 <= '1';
    wait for 9 ns;
    SW3 <= '0';
    wait for 311 ns;
    SW2 <= '1';
    wait for 557 ns;
    SW2 <= '0';
    wait for 401 ns;
    SW6 <= '1';
    wait for 467 ns;
    SW6 <= '0';
    wait for 1041 ns;
    HexB <= x"1";
    wait for 295 ns;
    SW6 <= '1';
    wait for 180 ns;
    HexA <= x"1";
    wait for 270 ns;
    SW6 <= '0';
    wait for 2957 ns;
    SW4 <= '0';
    wait for 328 ns;
    wait;
  end process;
end STIMULATOR;

-- Test Bench wrapper for stimulus and Model Under Test
library ieee, std;
use ieee.std_logic_1164.all;
library syncad_vhdl_lib;
use syncad_vhdl_lib.TBDefinitions.all;
-- Additional libraries used by Model Under Test.
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.NUMERIC_BIT.all;
use ieee.STD_LOGIC_ARITH.all;
-- End Additional libraries used by Model Under Test.

entity testbench is
end testbench;
architecture tbGeneratedCode of testbench is
  signal DATA_LCD : std_logic_vector(7 downto 4);
  signal LED : std_logic_vector(7 downto 0);
  signal HexA : std_logic_vector(3 downto 0);
  signal HexB : std_logic_vector(3 downto 0);
  signal CLK : std_logic;
  signal SW1 : std_logic;
  signal SW5 : std_logic;
  signal RS_LCD : std_logic;
  signal EN_LCD : std_logic;
  signal R_nW_LCD : std_logic;
  signal SW2 : std_logic;
  signal SW4 : std_logic;
  signal SW3 : std_logic;
  signal SW6 : std_logic;

  -- Stimulator instance

begin

  stimulus_0 : entity work.stimulus
    port map (DATA_LCD => DATA_LCD,
              LED => LED,
              HexA => HexA,
              HexB => HexB,
              CLK => CLK,
              SW1 => SW1,
              SW5 => SW5,
              RS_LCD => RS_LCD,
              EN_LCD => EN_LCD,
              R_nW_LCD => R_nW_LCD,
              SW2 => SW2,
              SW4 => SW4,
              SW3 => SW3,
              SW6 => SW6);

  -- Instantiation of Model Under Test.
  TOP_0 : entity work.TOP
    port map (CLK => CLK,
              RS_LCD => RS_LCD,
              DATA_LCD => DATA_LCD,
              EN_LCD => EN_LCD,
              R_nW_LCD => R_nW_LCD,
              LED => LED,
              HexA => HexA,
              HexB => HexB,
              SW1 => SW1,
              SW2 => SW2,
              SW3 => SW3,
              SW4 => SW4,
              SW5 => SW5,
              SW6 => SW6);
end tbGeneratedCode;