top.vhd

ACTEL A3P StartKit FPGA开发全套文挡（含测试源码）

-- Top2.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.NUMERIC_BIT.all;
use ieee.STD_LOGIC_ARITH.all;


entity TOP is

    port(CLK : in std_logic; --osc clock
    SW1 : in std_logic; --asyn_clr

    SW5 : in std_logic; --manual clock for LCD
    SW4 : in std_logic; --press sw4 for manual clock
     
    RS_LCD : out std_logic; --LCD signals
    DATA_LCD : out std_logic_vector(7 downto 4); --LCD signals
    EN_LCD : out std_logic; --LCD signals
    R_nW_LCD : out std_logic; --LCD signals 

    LED : out std_logic_vector(7 downto 0); --display from two counter
        
    HexA: in std_logic_vector(3 downto 0);
    HexB: in std_logic_vector(3 downto 0);
    SW2 : in std_logic; --updown for counter, press sw3 for down count
    SW3 : in std_logic; --asynchronous load
    SW6 : in std_logic);--press Sw7 for LED to switch between flashing and counting  
end TOP;

architecture DEF_ARCH of TOP is 


    component Data_Block
    port(Clock : in std_logic;
       DATA_LED: out std_logic_vector(7 downto 0);
       Updown : in std_logic;
       Aclr : in std_logic;
       Sload : in std_logic;
       Data_select: in std_logic;
       HexA: in std_logic_vector(3 downto 0);
       HexB: in std_logic_vector(3 downto 0));
    end component;

    component CLK_DIVIDER
        port(CLK, ACLR : in std_logic; DIVIDED_CLK1, DIVIDED_CLK2 : out std_logic);
    end component;

    component lcd
    Port ( lcd_data : out std_logic_vector (7 downto 4);
           clk        : in std_logic;
--		   clk_mode        : in std_logic;
		   reset      : in std_logic;  -- active high
		   lcd_enable : out std_logic;
           lcd_rs : out std_logic;
 		   lcd_rw : out std_logic);
    end component;


    --divided clock signal
    signal clk_internal1,clk_internal2: std_logic;
    --divided clock signal that goes to mux
    signal clk_internal_c: std_logic;

     --counter signals that go to the LCD and LED
    signal LCD_net: std_logic_vector (7 downto 4);
    signal lcd_rw, lcd_rs, lcd_en : std_logic;
    signal count_net: std_logic_vector (7 downto 0); 


begin 

--data to led
Data_Block_intance: Data_Block
      port map(Clock => clk_internal1, DATA_LED(7) => count_net(7), 
      DATA_LED(6) => count_net(6), DATA_LED(5) => count_net(5), 
      DATA_LED(4) => count_net(4), DATA_LED(3) => count_net(3), 
      DATA_LED(2) => count_net(2), DATA_LED(1) => count_net(1), 
      DATA_LED(0) => count_net(0),
      Updown => SW2, Aclr => SW1, Sload => SW3, Data_select => SW6,
      HexA(3) => HexA(3), HexA(2) => HexA(2), HexA(1) => HexA(1), 
      HexA(0) => HexA(0), HexB(3) => HexB(3), HexB(2) => HexB(2), 
      HexB(1) => HexB(1), HexB(0) => HexB(0));


--divide the 40 Mhz clock by 26
CLK_DIVIDER_intance : CLK_DIVIDER
      port map(CLK => CLK, ACLR => SW1, DIVIDED_CLK1 => clk_internal1, DIVIDED_CLK2 => clk_internal2);

--press SW4 to select manual clock for bebugging      
clk_led : process(SW4, SW5, clk_internal2)
        begin
	    if SW4='1' then
	    clk_internal_c <= SW5;
        else
        clk_internal_c <= clk_internal2 ;		
        end if;
end process clk_led;


lcd_instance: lcd
    port map ( lcd_data => LCD_net, clk => clk_internal_c, reset => SW1, 
    lcd_enable => lcd_en, lcd_rs => lcd_rs, lcd_rw => lcd_rw); 


clear_LCD_LED : process(SW2, LCD_net, lcd_rw, lcd_rs, count_net )
begin

if SW1='1' then
    R_nW_LCD <= '0';
    RS_LCD <= '0';
    EN_LCD <= '0';
    DATA_LCD(7) <='0';
    DATA_LCD(6) <='0';
    DATA_LCD(5) <='0';
    DATA_LCD(4) <='0';
    LED(7) <= '0';
    LED(6) <= '0';
    LED(5) <= '0';
    LED(4) <= '0';
    LED(3) <= '0';
    LED(2) <= '0';
    LED(1) <= '0';
    LED(0) <= '0';
else
    R_nW_LCD <= lcd_rw ;
    RS_LCD <= lcd_rs ;
    EN_LCD <= lcd_en;
    DATA_LCD(7) <=LCD_net(7);
    DATA_LCD(6) <=LCD_net(6);
    DATA_LCD(5) <=LCD_net(5);
    DATA_LCD(4) <=LCD_net(4);

    LED(7) <= count_net(7);
    LED(6) <= count_net(6);
    LED(5) <= count_net(5);
    LED(4) <= count_net(4);
    LED(3) <= count_net(3);
    LED(2) <= count_net(2);
    LED(1) <= count_net(1);
    LED(0) <= count_net(0);

end if;

end process clear_LCD_LED;


end DEF_ARCH;