excalibur.h

重要代码,FPGA CYCLONE FLASH DRIVER

// MAKE            =
// clockunit       = kHz
// delayunit       = us



// ------------------
// Parameters for altera_nios2 named cpu

// asp_debug                                       = 0
// asp_core_debug                                  = 0
// CPU_Architecture                                = nios2
// do_generate                                     = 1
// cpu_selection                                   = e
// CPU_Implementation                              = tiny
// cache_has_dcache                                = 0
// cache_has_icache                                = 0
// cache_dcache_size                               = 1024
// cache_icache_size                               = 2048
// include_debug                                   = 0
// include_trace                                   = 0
// include_oci                                     = 1
// debug_level                                     = 2
// oci_offchip_trace                               = 0
// oci_onchip_trace                                = 0
// oci_data_trace                                  = 0
// oci_trace_addr_width                            = 7
// oci_num_xbrk                                    = 0
// oci_num_dbrk                                    = 0
// oci_dbrk_trace                                  = 0
// oci_dbrk_pairs                                  = 0
// oci_num_pm                                      = 0
// oci_pm_width                                    = 40
// oci_debugreq_signals                            = 0
// hardware_multiply_present                       = 0
// remove_hardware_multiplier                      = 0
// hardware_divide_present                         = 0
// bht_ptr_sz                                      = 8
// reset_slave                                     = epcs_controller/epcs_control_port
// reset_offset                                    = 0x00000000
// exc_slave                                       = ext_ram/s1
// exc_offset                                      = 0x00000020
// break_slave                                     = cpu/jtag_debug_module
// break_offset                                    = 0x00000020
// break_slave_override                            =
// break_offset_override                           = 0x20
// legacy_sdk_support                              = 1
// altera_internal_test                            = 0
// full_waveform_signals                           = 0
// activate_model_checker                          = 0
// activate_trace                                  = 1
// activate_monitors                               = 1
// activate_test_end_checker                       = 0
// bit_31_bypass_dcache                            = 1
// always_bypass_dcache                            = 0
// always_encrypt                                  = 1
// hdl_sim_caches_cleared                          = 1
// clear_x_bits_ld_non_bypass                      = 1
// allow_full_address_range                        = 0
// consistent_synthesis                            = 0
// ibuf_ptr_sz                                     = 4
// jtb_ptr_sz                                      = 5
// performance_counters_present                    = 0
// performance_counters_width                      = 32
// ras_ptr_sz                                      = 4
// inst_decode_in_submodule                        = 0
// register_dependency_in_submodule                = 0
// source_operands_in_submodule                    = 0
// alu_in_submodule                                = 0
// stdata_in_submodule                             = 0
// shift_rot_2N_in_submodule                       = 0
// control_regs_in_submodule                       = 0
// M_inst_result_mux_in_submodule                  = 0
// dcache_load_aligner_in_submodule                = 0
// hardware_divide_in_submodule                    = 0
// mult_result_mux_in_submodule                    = 0
// shift_rotate_in_submodule                       = 0
// register_file_write_data_mux_in_submodule       = 0
// avalon_imaster_in_submodule                     = 0
// avalon_dmaster_in_submodule                     = 0
// avalon_load_aligner_in_submodule                = 0
// hbreak_test                                     = 0
// iss_trace_on                                    = 0
// iss_trace_warning                               = 1
// iss_trace_info                                  = 1
// iss_trace_disassembly                           = 0
// iss_trace_registers                             = 0
// iss_trace_instr_count                           = 0
// iss_software_debug                              = 0
// iss_software_debug_port                         = 9996
// iss_memory_dump_start                           =
// iss_memory_dump_end                             =
// Boot_Copier                                     = boot_loader_cfi.srec
// Boot_Copier_EPCS                                = boot_loader_epcs.srec
// CONSTANTS                                       =
// mult_cell_in_submodule                          =
// license_status                                  = encrypted
// germs_monitor_id                                = design(5)
// mainmem_slave                                   = ext_ram/s1
// datamem_slave                                   = ext_ram/s1
// maincomm_slave                                  = uart1/s1
// debugcomm_slave                                 = uart1/s1
// gui_include_tightly_coupled_instruction_masters = 0
// gui_num_tightly_coupled_instruction_masters     = 1
// gui_omit_avalon_data_master                     = 0
// gui_include_tightly_coupled_data_masters        = 0
// gui_num_tightly_coupled_data_masters            = 1
// num_tightly_coupled_instruction_masters         = 0
// num_tightly_coupled_data_masters                = 0
// cache_dcache_line_size                          = 4
// cache_icache_line_size                          = 32
// cache_dcache_bursts                             = 0
// cache_icache_burst_type                         = none
// cache_dcache_ram_block_type                     = AUTO
// cache_icache_ram_block_type                     = AUTO
// include_third_party_debug_port                  = 0
// oci_trigger_arming                              = 1
// oci_embedded_pll                                = 1
// gui_hardware_multiply_setting                   = no_mul_small_le_shift
// hardware_multiply_uses_les                      = 0
// hardware_multiply_omits_msw                     = 1
// hardware_multiply_impl                          = no_mul
// gui_hardware_divide_setting                     =
// altera_show_unreleased_features                 = 0
// gui_illegal_instructions_trap                   = 0
// illegal_instructions_trap                       = 0
// gui_illegal_memory_access_detection             = 0
// illegal_memory_access_detection                 = 0
// gui_branch_prediction_type                      = Automatic
// branch_prediction_type                          =
// bht_index_pc_only                               = 0
// shift_rot_impl                                  = small_le_shift
// gui_mmu_present                                 = 0
// mmu_present                                     = 0
// process_id_num_bits                             = 10
// dtlb_ptr_sz                                     = 7
// dtlb_num_ways                                   = 4
// udtlb_num_entries                               = 6
// itlb_ptr_sz                                     = 7
// itlb_num_ways                                   = 4
// uitlb_num_entries                               = 4
// fast_tlb_miss_exc_slave                         =
// fast_tlb_miss_exc_offset                        = 0x0
// cache_omit_dcache                               = 0
// cache_omit_icache                               = 0
// omit_instruction_master                         = 0
// omit_data_master                                = 0
// debug_simgen                                    = 0
// cpuid_sz                                        = 1
// cpuid_value                                     = 0

#ifndef _NIOS2_WSA_
#define _NIOS2_WSA_
#define NIOS2_ASP_DEBUG                                       0
#define NIOS2_ASP_CORE_DEBUG                                  0
#define NIOS2_CPU_ARCHITECTURE                                nios2
#define NIOS2_DO_GENERATE                                     1
#define NIOS2_CPU_SELECTION                                   e
#define NIOS2_CPU_IMPLEMENTATION                              tiny
#define NIOS2_CACHE_HAS_DCACHE                                0
#define NIOS2_CACHE_HAS_ICACHE                                0
#define NIOS2_CACHE_DCACHE_SIZE                               1024
#define NIOS2_CACHE_ICACHE_SIZE                               2048
#define NIOS2_INCLUDE_DEBUG                                   0
#define NIOS2_INCLUDE_TRACE                                   0
#define NIOS2_INCLUDE_OCI                                     1
#define NIOS2_DEBUG_LEVEL                                     2
#define NIOS2_OCI_OFFCHIP_TRACE                               0
#define NIOS2_OCI_ONCHIP_TRACE                                0
#define NIOS2_OCI_DATA_TRACE                                  0
#define NIOS2_OCI_TRACE_ADDR_WIDTH                            7
#define NIOS2_OCI_NUM_XBRK                                    0
#define NIOS2_OCI_NUM_DBRK                                    0
#define NIOS2_OCI_DBRK_TRACE                                  0
#define NIOS2_OCI_DBRK_PAIRS                                  0
#define NIOS2_OCI_NUM_PM                                      0
#define NIOS2_OCI_PM_WIDTH                                    40
#define NIOS2_OCI_DEBUGREQ_SIGNALS                            0
#define NIOS2_HARDWARE_MULTIPLY_PRESENT                       0
#define NIOS2_REMOVE_HARDWARE_MULTIPLIER                      0
#define NIOS2_HARDWARE_DIVIDE_PRESENT                         0
#define NIOS2_BHT_PTR_SZ                                      8
#define NIOS2_RESET_SLAVE                                     epcs_controller/epcs_control_port
#define NIOS2_RESET_OFFSET                                    0x00000000
#define NIOS2_EXC_SLAVE                                       ext_ram/s1
#define NIOS2_EXC_OFFSET                                      0x00000020
#define NIOS2_BREAK_SLAVE                                     cpu/jtag_debug_module
#define NIOS2_BREAK_OFFSET                                    0x00000020
#define NIOS2_BREAK_SLAVE_OVERRIDE
#define NIOS2_BREAK_OFFSET_OVERRIDE                           0x20
#define NIOS2_LEGACY_SDK_SUPPORT                              1
#define NIOS2_ALTERA_INTERNAL_TEST                            0
#define NIOS2_FULL_WAVEFORM_SIGNALS                           0
#define NIOS2_ACTIVATE_MODEL_CHECKER                          0
#define NIOS2_ACTIVATE_TRACE                                  1
#define NIOS2_ACTIVATE_MONITORS                               1
#define NIOS2_ACTIVATE_TEST_END_CHECKER                       0
#define NIOS2_BIT_31_BYPASS_DCACHE                            1
#define NIOS2_ALWAYS_BYPASS_DCACHE                            0
#define NIOS2_ALWAYS_ENCRYPT                                  1
#define NIOS2_HDL_SIM_CACHES_CLEARED                          1
#define NIOS2_CLEAR_X_BITS_LD_NON_BYPASS                      1
#define NIOS2_ALLOW_FULL_ADDRESS_RANGE                        0
#define NIOS2_CONSISTENT_SYNTHESIS                            0
#define NIOS2_IBUF_PTR_SZ                                     4
#define NIOS2_JTB_PTR_SZ                                      5
#define NIOS2_PERFORMANCE_COUNTERS_PRESENT                    0
#define NIOS2_PERFORMANCE_COUNTERS_WIDTH                      32
#define NIOS2_RAS_PTR_SZ                                      4
#define NIOS2_INST_DECODE_IN_SUBMODULE                        0
#define NIOS2_REGISTER_DEPENDENCY_IN_SUBMODULE                0
#define NIOS2_SOURCE_OPERANDS_IN_SUBMODULE                    0
#define NIOS2_ALU_IN_SUBMODULE                                0
#define NIOS2_STDATA_IN_SUBMODULE                             0
#define NIOS2_SHIFT_ROT_2N_IN_SUBMODULE                       0
#define NIOS2_CONTROL_REGS_IN_SUBMODULE                       0
#define NIOS2_M_INST_RESULT_MUX_IN_SUBMODULE                  0
#define NIOS2_DCACHE_LOAD_ALIGNER_IN_SUBMODULE                0
#define NIOS2_HARDWARE_DIVIDE_IN_SUBMODULE                    0
#define NIOS2_MULT_RESULT_MUX_IN_SUBMODULE                    0
#define NIOS2_SHIFT_ROTATE_IN_SUBMODULE                       0
#define NIOS2_REGISTER_FILE_WRITE_DATA_MUX_IN_SUBMODULE       0
#define NIOS2_AVALON_IMASTER_IN_SUBMODULE                     0
#define NIOS2_AVALON_DMASTER_IN_SUBMODULE                     0
#define NIOS2_AVALON_LOAD_ALIGNER_IN_SUBMODULE                0
#define NIOS2_HBREAK_TEST                                     0
#define NIOS2_ISS_TRACE_ON                                    0
#define NIOS2_ISS_TRACE_WARNING                               1
#define NIOS2_ISS_TRACE_INFO                                  1
#define NIOS2_ISS_TRACE_DISASSEMBLY                           0
#define NIOS2_ISS_TRACE_REGISTERS                             0
#define NIOS2_ISS_TRACE_INSTR_COUNT                           0
#define NIOS2_ISS_SOFTWARE_DEBUG                              0
#define NIOS2_ISS_SOFTWARE_DEBUG_PORT                         9996
#define NIOS2_ISS_MEMORY_DUMP_START
#define NIOS2_ISS_MEMORY_DUMP_END
#define NIOS2_BOOT_COPIER                                     boot_loader_cfi.srec
#define NIOS2_BOOT_COPIER_EPCS                                boot_loader_epcs.srec
#define NIOS2_CONSTANTS
#define NIOS2_MULT_CELL_IN_SUBMODULE
#define NIOS2_LICENSE_STATUS                                  encrypted
#define NIOS2_GERMS_MONITOR_ID                                design(5)
#define NIOS2_MAINMEM_SLAVE                                   ext_ram/s1
#define NIOS2_DATAMEM_SLAVE                                   ext_ram/s1
#define NIOS2_MAINCOMM_SLAVE                                  uart1/s1
#define NIOS2_DEBUGCOMM_SLAVE                                 uart1/s1
#define NIOS2_GUI_INCLUDE_TIGHTLY_COUPLED_INSTRUCTION_MASTERS 0
#define NIOS2_GUI_NUM_TIGHTLY_COUPLED_INSTRUCTION_MASTERS     1
#define NIOS2_GUI_OMIT_AVALON_DATA_MASTER                     0
#define NIOS2_GUI_INCLUDE_TIGHTLY_COUPLED_DATA_MASTERS        0
#define NIOS2_GUI_NUM_TIGHTLY_COUPLED_DATA_MASTERS            1
#define NIOS2_NUM_TIGHTLY_COUPLED_INSTRUCTION_MASTERS         0
#define NIOS2_NUM_TIGHTLY_COUPLED_DATA_MASTERS                0
#define NIOS2_CACHE_DCACHE_LINE_SIZE                          4
#define NIOS2_CACHE_ICACHE_LINE_SIZE                          32
#define NIOS2_CACHE_DCACHE_BURSTS                             0
#define NIOS2_CACHE_ICACHE_BURST_TYPE                         none
#define NIOS2_CACHE_DCACHE_RAM_BLOCK_TYPE                     AUTO
#define NIOS2_CACHE_ICACHE_RAM_BLOCK_TYPE                     AUTO
#define NIOS2_INCLUDE_THIRD_PARTY_DEBUG_PORT                  0
#define NIOS2_OCI_TRIGGER_ARMING                              1
#define NIOS2_OCI_EMBEDDED_PLL                                1
#define NIOS2_GUI_HARDWARE_MULTIPLY_SETTING                   no_mul_small_le_shift
#define NIOS2_HARDWARE_MULTIPLY_USES_LES                      0
#define NIOS2_HARDWARE_MULTIPLY_OMITS_MSW                     1
#define NIOS2_HARDWARE_MULTIPLY_IMPL                          no_mul
#define NIOS2_GUI_HARDWARE_DIVIDE_SETTING
#define NIOS2_ALTERA_SHOW_UNRELEASED_FEATURES                 0
#define NIOS2_GUI_ILLEGAL_INSTRUCTIONS_TRAP                   0
#define NIOS2_ILLEGAL_INSTRUCTIONS_TRAP                       0
#define NIOS2_GUI_ILLEGAL_MEMORY_ACCESS_DETECTION             0
#define NIOS2_ILLEGAL_MEMORY_ACCESS_DETECTION                 0
#define NIOS2_GUI_BRANCH_PREDICTION_TYPE                      Automatic
#define NIOS2_BRANCH_PREDICTION_TYPE
#define NIOS2_BHT_INDEX_PC_ONLY                               0
#define NIOS2_SHIFT_ROT_IMPL                                  small_le_shift
#define NIOS2_GUI_MMU_PRESENT                                 0
#define NIOS2_MMU_PRESENT                                     0
#define NIOS2_PROCESS_ID_NUM_BITS                             10
#define NIOS2_DTLB_PTR_SZ                                     7
#define NIOS2_DTLB_NUM_WAYS                                   4
#define NIOS2_UDTLB_NUM_ENTRIES                               6
#define NIOS2_ITLB_PTR_SZ                                     7
#define NIOS2_ITLB_NUM_WAYS                                   4
#define NIOS2_UITLB_NUM_ENTRIES                               4
#define NIOS2_FAST_TLB_MISS_EXC_SLAVE
#define NIOS2_FAST_TLB_MISS_EXC_OFFSET                        0x0
#define NIOS2_CACHE_OMIT_DCACHE                               0
#define NIOS2_CACHE_OMIT_ICACHE                               0
#define NIOS2_OMIT_INSTRUCTION_MASTER                         0
#define NIOS2_OMIT_DATA_MASTER                                0
#define NIOS2_DEBUG_SIMGEN                                    0
#define NIOS2_CPUID_SZ                                        1
#define NIOS2_CPUID_VALUE                                     0
#endif /* _NIOS2_WSA_ */



// ------------------
// Parameters for altera_nios_dev_kit_stratix_edition_sram2 named ext_ram

// sram_memory_size  = 1024
// sram_memory_units = 1024
// sram_data_width   = 32
// MAKE              =
// contents_info     =



// ------------------
// Parameters for altera_avalon_cfi_flash named cfi_flash_0

// Setup_Value     = 40
// Wait_Value      = 120
// Hold_Value      = 40
// Timing_Units    = ns
// Unit_Multiplier = 1
// Size            = 2097152
// MAKE            =



#ifdef __cplusplus
}
#endif

#endif //_excalibur_

// end of file