excalibur.h

重要代码,FPGA CYCLONE FLASH DRIVER

// gui_hardware_divide_setting                     =
// altera_show_unreleased_features                 = 0
// gui_illegal_instructions_trap                   = 0
// illegal_instructions_trap                       = 0
// gui_illegal_memory_access_detection             = 0
// illegal_memory_access_detection                 = 0
// gui_branch_prediction_type                      = Automatic
// branch_prediction_type                          =
// bht_index_pc_only                               = 0
// shift_rot_impl                                  = small_le_shift
// gui_mmu_present                                 = 0
// mmu_present                                     = 0
// process_id_num_bits                             = 10
// dtlb_ptr_sz                                     = 7
// dtlb_num_ways                                   = 4
// udtlb_num_entries                               = 6
// itlb_ptr_sz                                     = 7
// itlb_num_ways                                   = 4
// uitlb_num_entries                               = 4
// fast_tlb_miss_exc_slave                         =
// fast_tlb_miss_exc_offset                        = 0x0
// cache_omit_dcache                               = 0
// cache_omit_icache                               = 0
// omit_instruction_master                         = 0
// omit_data_master                                = 0
// debug_simgen                                    = 0
// cpuid_sz                                        = 1
// cpuid_value                                     = 0

#ifndef _NIOS2_WSA_
#define _NIOS2_WSA_
#define NIOS2_ASP_DEBUG                                       0
#define NIOS2_ASP_CORE_DEBUG                                  0
#define NIOS2_CPU_ARCHITECTURE                                nios2
#define NIOS2_DO_GENERATE                                     1
#define NIOS2_CPU_SELECTION                                   e
#define NIOS2_CPU_IMPLEMENTATION                              tiny
#define NIOS2_CACHE_HAS_DCACHE                                0
#define NIOS2_CACHE_HAS_ICACHE                                0
#define NIOS2_CACHE_DCACHE_SIZE                               1024
#define NIOS2_CACHE_ICACHE_SIZE                               2048
#define NIOS2_INCLUDE_DEBUG                                   0
#define NIOS2_INCLUDE_TRACE                                   0
#define NIOS2_INCLUDE_OCI                                     1
#define NIOS2_DEBUG_LEVEL                                     2
#define NIOS2_OCI_OFFCHIP_TRACE                               0
#define NIOS2_OCI_ONCHIP_TRACE                                0
#define NIOS2_OCI_DATA_TRACE                                  0
#define NIOS2_OCI_TRACE_ADDR_WIDTH                            7
#define NIOS2_OCI_NUM_XBRK                                    0
#define NIOS2_OCI_NUM_DBRK                                    0
#define NIOS2_OCI_DBRK_TRACE                                  0
#define NIOS2_OCI_DBRK_PAIRS                                  0
#define NIOS2_OCI_NUM_PM                                      0
#define NIOS2_OCI_PM_WIDTH                                    40
#define NIOS2_OCI_DEBUGREQ_SIGNALS                            0
#define NIOS2_HARDWARE_MULTIPLY_PRESENT                       0
#define NIOS2_REMOVE_HARDWARE_MULTIPLIER                      0
#define NIOS2_HARDWARE_DIVIDE_PRESENT                         0
#define NIOS2_BHT_PTR_SZ                                      8
#define NIOS2_RESET_SLAVE                                     epcs_controller/epcs_control_port
#define NIOS2_RESET_OFFSET                                    0x00000000
#define NIOS2_EXC_SLAVE                                       ext_ram/s1
#define NIOS2_EXC_OFFSET                                      0x00000020
#define NIOS2_BREAK_SLAVE                                     cpu/jtag_debug_module
#define NIOS2_BREAK_OFFSET                                    0x00000020
#define NIOS2_BREAK_SLAVE_OVERRIDE
#define NIOS2_BREAK_OFFSET_OVERRIDE                           0x20
#define NIOS2_LEGACY_SDK_SUPPORT                              1
#define NIOS2_ALTERA_INTERNAL_TEST                            0
#define NIOS2_FULL_WAVEFORM_SIGNALS                           0
#define NIOS2_ACTIVATE_MODEL_CHECKER                          0
#define NIOS2_ACTIVATE_TRACE                                  1
#define NIOS2_ACTIVATE_MONITORS                               1
#define NIOS2_ACTIVATE_TEST_END_CHECKER                       0
#define NIOS2_BIT_31_BYPASS_DCACHE                            1
#define NIOS2_ALWAYS_BYPASS_DCACHE                            0
#define NIOS2_ALWAYS_ENCRYPT                                  1
#define NIOS2_HDL_SIM_CACHES_CLEARED                          1
#define NIOS2_CLEAR_X_BITS_LD_NON_BYPASS                      1
#define NIOS2_ALLOW_FULL_ADDRESS_RANGE                        0
#define NIOS2_CONSISTENT_SYNTHESIS                            0
#define NIOS2_IBUF_PTR_SZ                                     4
#define NIOS2_JTB_PTR_SZ                                      5
#define NIOS2_PERFORMANCE_COUNTERS_PRESENT                    0
#define NIOS2_PERFORMANCE_COUNTERS_WIDTH                      32
#define NIOS2_RAS_PTR_SZ                                      4
#define NIOS2_INST_DECODE_IN_SUBMODULE                        0
#define NIOS2_REGISTER_DEPENDENCY_IN_SUBMODULE                0
#define NIOS2_SOURCE_OPERANDS_IN_SUBMODULE                    0
#define NIOS2_ALU_IN_SUBMODULE                                0
#define NIOS2_STDATA_IN_SUBMODULE                             0
#define NIOS2_SHIFT_ROT_2N_IN_SUBMODULE                       0
#define NIOS2_CONTROL_REGS_IN_SUBMODULE                       0
#define NIOS2_M_INST_RESULT_MUX_IN_SUBMODULE                  0
#define NIOS2_DCACHE_LOAD_ALIGNER_IN_SUBMODULE                0
#define NIOS2_HARDWARE_DIVIDE_IN_SUBMODULE                    0
#define NIOS2_MULT_RESULT_MUX_IN_SUBMODULE                    0
#define NIOS2_SHIFT_ROTATE_IN_SUBMODULE                       0
#define NIOS2_REGISTER_FILE_WRITE_DATA_MUX_IN_SUBMODULE       0
#define NIOS2_AVALON_IMASTER_IN_SUBMODULE                     0
#define NIOS2_AVALON_DMASTER_IN_SUBMODULE                     0
#define NIOS2_AVALON_LOAD_ALIGNER_IN_SUBMODULE                0
#define NIOS2_HBREAK_TEST                                     0
#define NIOS2_ISS_TRACE_ON                                    0
#define NIOS2_ISS_TRACE_WARNING                               1
#define NIOS2_ISS_TRACE_INFO                                  1
#define NIOS2_ISS_TRACE_DISASSEMBLY                           0
#define NIOS2_ISS_TRACE_REGISTERS                             0
#define NIOS2_ISS_TRACE_INSTR_COUNT                           0
#define NIOS2_ISS_SOFTWARE_DEBUG                              0
#define NIOS2_ISS_SOFTWARE_DEBUG_PORT                         9996
#define NIOS2_ISS_MEMORY_DUMP_START
#define NIOS2_ISS_MEMORY_DUMP_END
#define NIOS2_BOOT_COPIER                                     boot_loader_cfi.srec
#define NIOS2_BOOT_COPIER_EPCS                                boot_loader_epcs.srec
#define NIOS2_CONSTANTS
#define NIOS2_MULT_CELL_IN_SUBMODULE
#define NIOS2_LICENSE_STATUS                                  encrypted
#define NIOS2_GERMS_MONITOR_ID                                design(5)
#define NIOS2_MAINMEM_SLAVE                                   ext_ram/s1
#define NIOS2_DATAMEM_SLAVE                                   ext_ram/s1
#define NIOS2_MAINCOMM_SLAVE                                  uart1/s1
#define NIOS2_DEBUGCOMM_SLAVE                                 uart1/s1
#define NIOS2_GUI_INCLUDE_TIGHTLY_COUPLED_INSTRUCTION_MASTERS 0
#define NIOS2_GUI_NUM_TIGHTLY_COUPLED_INSTRUCTION_MASTERS     1
#define NIOS2_GUI_OMIT_AVALON_DATA_MASTER                     0
#define NIOS2_GUI_INCLUDE_TIGHTLY_COUPLED_DATA_MASTERS        0
#define NIOS2_GUI_NUM_TIGHTLY_COUPLED_DATA_MASTERS            1
#define NIOS2_NUM_TIGHTLY_COUPLED_INSTRUCTION_MASTERS         0
#define NIOS2_NUM_TIGHTLY_COUPLED_DATA_MASTERS                0
#define NIOS2_CACHE_DCACHE_LINE_SIZE                          4
#define NIOS2_CACHE_ICACHE_LINE_SIZE                          32
#define NIOS2_CACHE_DCACHE_BURSTS                             0
#define NIOS2_CACHE_ICACHE_BURST_TYPE                         none
#define NIOS2_CACHE_DCACHE_RAM_BLOCK_TYPE                     AUTO
#define NIOS2_CACHE_ICACHE_RAM_BLOCK_TYPE                     AUTO
#define NIOS2_INCLUDE_THIRD_PARTY_DEBUG_PORT                  0
#define NIOS2_OCI_TRIGGER_ARMING                              1
#define NIOS2_OCI_EMBEDDED_PLL                                1
#define NIOS2_GUI_HARDWARE_MULTIPLY_SETTING                   no_mul_small_le_shift
#define NIOS2_HARDWARE_MULTIPLY_USES_LES                      0
#define NIOS2_HARDWARE_MULTIPLY_OMITS_MSW                     1
#define NIOS2_HARDWARE_MULTIPLY_IMPL                          no_mul
#define NIOS2_GUI_HARDWARE_DIVIDE_SETTING
#define NIOS2_ALTERA_SHOW_UNRELEASED_FEATURES                 0
#define NIOS2_GUI_ILLEGAL_INSTRUCTIONS_TRAP                   0
#define NIOS2_ILLEGAL_INSTRUCTIONS_TRAP                       0
#define NIOS2_GUI_ILLEGAL_MEMORY_ACCESS_DETECTION             0
#define NIOS2_ILLEGAL_MEMORY_ACCESS_DETECTION                 0
#define NIOS2_GUI_BRANCH_PREDICTION_TYPE                      Automatic
#define NIOS2_BRANCH_PREDICTION_TYPE
#define NIOS2_BHT_INDEX_PC_ONLY                               0
#define NIOS2_SHIFT_ROT_IMPL                                  small_le_shift
#define NIOS2_GUI_MMU_PRESENT                                 0
#define NIOS2_MMU_PRESENT                                     0
#define NIOS2_PROCESS_ID_NUM_BITS                             10
#define NIOS2_DTLB_PTR_SZ                                     7
#define NIOS2_DTLB_NUM_WAYS                                   4
#define NIOS2_UDTLB_NUM_ENTRIES                               6
#define NIOS2_ITLB_PTR_SZ                                     7
#define NIOS2_ITLB_NUM_WAYS                                   4
#define NIOS2_UITLB_NUM_ENTRIES                               4
#define NIOS2_FAST_TLB_MISS_EXC_SLAVE
#define NIOS2_FAST_TLB_MISS_EXC_OFFSET                        0x0
#define NIOS2_CACHE_OMIT_DCACHE                               0
#define NIOS2_CACHE_OMIT_ICACHE                               0
#define NIOS2_OMIT_INSTRUCTION_MASTER                         0
#define NIOS2_OMIT_DATA_MASTER                                0
#define NIOS2_DEBUG_SIMGEN                                    0
#define NIOS2_CPUID_SZ                                        1
#define NIOS2_CPUID_VALUE                                     0
#endif /* _NIOS2_WSA_ */



// ------------------
// Parameters for altera_avalon_timer named timer1

// always_run           = 0
// fixed_period         = 0
// snapshot             = 1
// period               = 1
// period_units         = ms
// reset_output         = 0
// timeout_pulse_output = 0
// mult                 = 0.001



// ------------------
// Parameters for altera_avalon_uart named uart2

// baud             = 9600
// data_bits        = 8
// fixed_baud       = 1
// parity           = N
// stop_bits        = 1
// use_cts_rts      = 0
// use_eop_register = 0
// sim_true_baud    = 0
// sim_char_stream  =



// ------------------
// Parameters for altera_avalon_pio named led_pio

// Do_Test_Bench_Wiring = 0
// Driven_Sim_Value     = 0x0000
// has_tri              = 0
// has_out              = 1
// has_in               = 0
// capture              = 0
// edge_type            = NONE
// irq_type             = NONE



// ------------------
// Parameters for altera_avalon_sysid named sysid

// id        = 1625977725u
// timestamp = 1145434281u
// MAKE      =



// ------------------
// Parameters for altera_avalon_jtag_uart named jtag_uart

// write_depth                               = 64
// read_depth                                = 64
// write_threshold                           = 8
// read_threshold                            = 8
// read_char_stream                          =
// showascii                                 = 1
// read_le                                   = 0
// write_le                                  = 0
// altera_show_unreleased_jtag_uart_features = 0



// ------------------
// Parameters for altera_avalon_pll named pll_0

// locked        = None
// areset        = None
// pllena        = None
// pfdena        = None
// Config_Done   = 1
// UI_CONTROL    =
// ALTPLL_PORTS  =
// CLOCK_INFO    =
// CLOCK_SOURCES =
// CNX_INFO      =



// ------------------
// Parameters for altera_avalon_timer named timer_dram

// always_run           = 0
// fixed_period         = 0
// snapshot             = 1
// period               = 1
// period_units         = ms
// reset_output         = 0
// timeout_pulse_output = 0
// mult                 = 0.001



// ------------------
// Parameters for altera_avalon_user_defined_interface named idt7132

// Imported_Wait         = 0
// Nios_Gen_Waits        = 1
// Simulate_Imported_HDL = 0
// Port_Type             = Avalon Slave
// HDL_Import            = 0
// Timing_Units          = ns
// Unit_Multiplier       = 1
// Setup_Value           = 50
// Hold_Value            = 50
// Wait_Value            = 50
// Address_Width         = 32
// Module_List           =
// Show_Streaming        = 0
// Show_Latency          = 0
// Technology            = User Logic
// File_Count            = 0
// Port_Count            = 5
// Component_Desc        = idt7132
// Module_Name           =



// ------------------
// Parameters for altera_avalon_onchip_memory named onchip_rom

// Writeable                         = 1
// Size_Value                        = 4
// Size_Multiple                     = 1024
// Contents                          = blank
// Shrink_to_fit_contents            = 0
// use_altsyncram                    = 1
// use_ram_block_type                = M4K
// altsyncram_ram_block_type         = AUTO
// dual_port                         = 0
// allow_mram_sim_contents_only_file = 0
// CONTENTS                          = srec



// ------------------
// Parameters for altera_avalon_epcs_flash_controller named epcs_controller

// databits        = 8
// targetclock     = 20
// clockunits      = MHz
// clockmult       = 1000000
// numslaves       = 1
// ismaster        = 1
// clockpolarity   = 0
// clockphase      = 0
// lsbfirst        = 0
// extradelay      = 1
// targetssdelay   = 100
// delayunits      = us
// delaymult       = 1e-006
// prefix          = epcs_
// register_offset = 0x200