excalibur.h

重要代码,FPGA CYCLONE FLASH DRIVER

// PIO Peripheral

// PIO Registers
typedef volatile struct
	{
	int np_piodata;          // read/write, up to 32 bits
	int np_piodirection;     // write/readable, up to 32 bits, 1->output bit
	int np_piointerruptmask; // write/readable, up to 32 bits, 1->enable interrupt
	int np_pioedgecapture;   // read, up to 32 bits, cleared by any write
	} np_pio;

// PIO Routines
void nr_pio_showhex(int value); // shows low byte on pio named na_seven_seg_pio



#define nk_epcs_64K 0
#define nk_epcs_1M 0
#define nk_epcs_4M 1

// EPCS Registers
typedef volatile struct
  {
  int np_dummy[256];       // EPCS component fills lower 1k with code
  int np_epcsrxdata;       // Read-only, 1-16 bit
  int np_epcstxdata;       // Write-only, same width as rxdata
  int np_epcsstatus;       // Read-only, 9-bit
  int np_epcscontrol;      // Read/Write, 9-bit
  int np_epcsreserved;     // reserved
  int np_epcsslaveselect;  // Read/Write, 1-16 bit, master only
  int np_epcsendofpacket;  // Read/write, same width as txdata, rxdata.
  } np_epcs;

// EPCS Status Register Bits
enum
  {
  np_epcsstatus_eop_bit  = 9,
  np_epcsstatus_e_bit    = 8,
  np_epcsstatus_rrdy_bit = 7,
  np_epcsstatus_trdy_bit = 6,
  np_epcsstatus_tmt_bit  = 5,
  np_epcsstatus_toe_bit  = 4,
  np_epcsstatus_roe_bit  = 3,

  np_epcsstatus_eop_mask  = (1 << 9),
  np_epcsstatus_e_mask    = (1 << 8),
  np_epcsstatus_rrdy_mask = (1 << 7),
  np_epcsstatus_trdy_mask = (1 << 6),
  np_epcsstatus_tmt_mask  = (1 << 5),
  np_epcsstatus_toe_mask  = (1 << 4),
  np_epcsstatus_roe_mask  = (1 << 3),
  };

// EPCS Control Register Bits
enum
  {
  np_epcscontrol_sso_bit   = 10,
  np_epcscontrol_ieop_bit  = 9,
  np_epcscontrol_ie_bit    = 8,
  np_epcscontrol_irrdy_bit = 7,
  np_epcscontrol_itrdy_bit = 6,
  np_epcscontrol_itoe_bit  = 4,
  np_epcscontrol_iroe_bit  = 3,

  np_epcscontrol_sso_mask   = (1 << 10),
  np_epcscontrol_ieop_mask  = (1 << 9),
  np_epcscontrol_ie_mask    = (1 << 8),
  np_epcscontrol_irrdy_mask = (1 << 7),
  np_epcscontrol_itrdy_mask = (1 << 6),
  np_epcscontrol_itoe_mask  = (1 << 4),
  np_epcscontrol_iroe_mask  = (1 << 3),
  };


//EPCS memory definitions
#if nk_epcs_64K
#define na_epcs_bulk_size   (0x2000)
#define na_epcs_sector_size (na_epcs_bulk_size >> 2)
#define na_epcs_page_size   0x20

#elif nk_epcs_1M
#define na_epcs_bulk_size   (0x20000)
#define na_epcs_sector_size (na_epcs_bulk_size >> 2)
#define na_epcs_page_size   0x100

#elif nk_epcs_4M
#define na_epcs_bulk_size   (0x80000)
#define na_epcs_sector_size (na_epcs_bulk_size >> 3)
#define na_epcs_page_size   0x100
#endif

//EPCS memory instructions
#define na_epcs_read    (unsigned char)0x03
#define na_epcs_write   (unsigned char)0x02
#define na_epcs_wren    (unsigned char)0x06
#define na_epcs_wrdi    (unsigned char)0x04
#define na_epcs_rdsr    (unsigned char)0x05
#define na_epcs_wrsr    (unsigned char)0x01
#define na_epcs_se      (unsigned char)0xd8
#define na_epcs_be      (unsigned char)0xc7
#define na_epcs_dp      (unsigned char)0xb9

//EPCS memory status register bit masks
#if (na_epcs_64K) || (na_epcs_1M)
#define na_epcs_bp      (unsigned char)0xc
#else
#define na_epcs_bp      (unsigned char)0x1c
#endif
#define na_epcs_wel     (unsigned char)0x2
#define na_epcs_wip     (unsigned char)0x1

//EPCS function error codes
#define na_epcs_success                 0
#define na_epcs_err_device_not_present  1
#define na_epcs_err_device_not_ready    2
#define na_epcs_err_timedout            3
#define na_epcs_err_write_failed        4
#define na_epcs_invalid_config          5

//EPCS protection masks
#define na_epcs_protect_none        0
#if (na_epcs_64K) || (na_epcs_1M)
#define na_epcs_protect_top_quarter 0x4
#define na_epcs_protect_top_half    0x8
#define na_epcs_protect_all         0xc
#else
#define na_epcs_protect_top_eighth  0x4
#define na_epcs_protect_top_quarter 0x8
#define na_epcs_protect_top_half    0xc
#define na_epcs_protect_all         0x10
#endif

//EPCS macros
//returns the protect bits shifted into the lsbs
#define nm_epcs_prot_sect(t) ((t & na_epcs_bp) >> 2)

//EPCS library routines
//

extern unsigned char nr_epcs_read_status ();
extern unsigned long nr_epcs_lowest_protected_address();
extern int nr_epcs_write_status (unsigned char value);
extern int nr_epcs_protect_region (int bpcode);
extern int nr_epcs_read_byte (unsigned long address, unsigned char *data);
extern int nr_epcs_write_byte (unsigned long address, unsigned char data);
extern int nr_epcs_erase_sector (unsigned long address);
extern int nr_epcs_erase_bulk ();
extern int nr_epcs_read_buffer (unsigned long address, int length, unsigned char *data);
extern int nr_epcs_write_page (unsigned long address, int length, unsigned char *data);
extern int nr_epcs_write_buffer (unsigned long address, int length, unsigned char *data);
extern int nr_epcs_address_past_config (unsigned long *addr);
        

// Nios Flash Memory Routines

// All routines take a "flash base" parameter.
// If -1 is supplied,
// nasys_main_flash is used.

int nr_flash_erase_sector
		(
			unsigned short *flash_base,
  			unsigned short *sector_address
		);

int nr_flash_erase
		(
			unsigned short *flash_base
		);

int nr_flash_write
		(
			unsigned short *flash_base,
  			unsigned short *address,
			unsigned short value
		);

int nr_flash_write_buffer
		(
			unsigned short *flash_base,
  			unsigned short *start_address,
  			unsigned short *buffer,
			int halfword_count
		);





// ===========================================================
// Parameters for Each Peripheral, Excerpted From The PTF File



// ------------------
// Parameters for altera_avalon_uart named uart1

// baud             = 9600
// data_bits        = 8
// fixed_baud       = 1
// parity           = N
// stop_bits        = 1
// use_cts_rts      = 0
// use_eop_register = 0
// sim_true_baud    = 0
// sim_char_stream  =



// ------------------
// Parameters for altera_plugs_library named altera_plugs_library

// CONSTANTS =



// ------------------
// Parameters for altera_nios2 named cpu

// asp_debug                                       = 0
// asp_core_debug                                  = 0
// CPU_Architecture                                = nios2
// do_generate                                     = 1
// cpu_selection                                   = e
// CPU_Implementation                              = tiny
// cache_has_dcache                                = 0
// cache_has_icache                                = 0
// cache_dcache_size                               = 1024
// cache_icache_size                               = 2048
// include_debug                                   = 0
// include_trace                                   = 0
// include_oci                                     = 1
// debug_level                                     = 2
// oci_offchip_trace                               = 0
// oci_onchip_trace                                = 0
// oci_data_trace                                  = 0
// oci_trace_addr_width                            = 7
// oci_num_xbrk                                    = 0
// oci_num_dbrk                                    = 0
// oci_dbrk_trace                                  = 0
// oci_dbrk_pairs                                  = 0
// oci_num_pm                                      = 0
// oci_pm_width                                    = 40
// oci_debugreq_signals                            = 0
// hardware_multiply_present                       = 0
// remove_hardware_multiplier                      = 0
// hardware_divide_present                         = 0
// bht_ptr_sz                                      = 8
// reset_slave                                     = epcs_controller/epcs_control_port
// reset_offset                                    = 0x00000000
// exc_slave                                       = ext_ram/s1
// exc_offset                                      = 0x00000020
// break_slave                                     = cpu/jtag_debug_module
// break_offset                                    = 0x00000020
// break_slave_override                            =
// break_offset_override                           = 0x20
// legacy_sdk_support                              = 1
// altera_internal_test                            = 0
// full_waveform_signals                           = 0
// activate_model_checker                          = 0
// activate_trace                                  = 1
// activate_monitors                               = 1
// activate_test_end_checker                       = 0
// bit_31_bypass_dcache                            = 1
// always_bypass_dcache                            = 0
// always_encrypt                                  = 1
// hdl_sim_caches_cleared                          = 1
// clear_x_bits_ld_non_bypass                      = 1
// allow_full_address_range                        = 0
// consistent_synthesis                            = 0
// ibuf_ptr_sz                                     = 4
// jtb_ptr_sz                                      = 5
// performance_counters_present                    = 0
// performance_counters_width                      = 32
// ras_ptr_sz                                      = 4
// inst_decode_in_submodule                        = 0
// register_dependency_in_submodule                = 0
// source_operands_in_submodule                    = 0
// alu_in_submodule                                = 0
// stdata_in_submodule                             = 0
// shift_rot_2N_in_submodule                       = 0
// control_regs_in_submodule                       = 0
// M_inst_result_mux_in_submodule                  = 0
// dcache_load_aligner_in_submodule                = 0
// hardware_divide_in_submodule                    = 0
// mult_result_mux_in_submodule                    = 0
// shift_rotate_in_submodule                       = 0
// register_file_write_data_mux_in_submodule       = 0
// avalon_imaster_in_submodule                     = 0
// avalon_dmaster_in_submodule                     = 0
// avalon_load_aligner_in_submodule                = 0
// hbreak_test                                     = 0
// iss_trace_on                                    = 0
// iss_trace_warning                               = 1
// iss_trace_info                                  = 1
// iss_trace_disassembly                           = 0
// iss_trace_registers                             = 0
// iss_trace_instr_count                           = 0
// iss_software_debug                              = 0
// iss_software_debug_port                         = 9996
// iss_memory_dump_start                           =
// iss_memory_dump_end                             =
// Boot_Copier                                     = boot_loader_cfi.srec
// Boot_Copier_EPCS                                = boot_loader_epcs.srec
// CONSTANTS                                       =
// mult_cell_in_submodule                          =
// license_status                                  = encrypted
// germs_monitor_id                                = design(5)
// mainmem_slave                                   = ext_ram/s1
// datamem_slave                                   = ext_ram/s1
// maincomm_slave                                  = uart1/s1
// debugcomm_slave                                 = uart1/s1
// gui_include_tightly_coupled_instruction_masters = 0
// gui_num_tightly_coupled_instruction_masters     = 1
// gui_omit_avalon_data_master                     = 0
// gui_include_tightly_coupled_data_masters        = 0
// gui_num_tightly_coupled_data_masters            = 1
// num_tightly_coupled_instruction_masters         = 0
// num_tightly_coupled_data_masters                = 0
// cache_dcache_line_size                          = 4
// cache_icache_line_size                          = 32
// cache_dcache_bursts                             = 0
// cache_icache_burst_type                         = none
// cache_dcache_ram_block_type                     = AUTO
// cache_icache_ram_block_type                     = AUTO
// include_third_party_debug_port                  = 0
// oci_trigger_arming                              = 1
// oci_embedded_pll                                = 1
// gui_hardware_multiply_setting                   = no_mul_small_le_shift
// hardware_multiply_uses_les                      = 0
// hardware_multiply_omits_msw                     = 1
// hardware_multiply_impl                          = no_mul