📄 excalibur.h
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/* * File: excalibur.h * * This file is a machine generated address map * for a CPU named cpu. * F:/interrupt_flow/new_04010_20/fifth_nios2_system.ptf * Generated: 2006.07.28 12:36:24 DO NOT MODIFY THIS FILE Changing this file will have subtle consequences which will almost certainly lead to a nonfunctioning system. If you do modify this file, you MUST change both excalibur.h, excalibur.s, and excalibur.mk identically. Or better yet: DO NOT MODIFY THIS FILE */#ifndef _excalibur_#define _excalibur_// Legacy SDK will not be supported for Nios II in version 6.0 and beyond.// Please migrate your software to use the HAL System Library.// See the Nios II Software Developer's Handbook.#include <stdio.h>#include <stdlib.h>#ifdef __cplusplusextern "C" {#endif// The Memory Map#define na_uart1 ((np_uart *) 0x00000000) // altera_avalon_uart#define na_uart1_base 0x00000000#define na_uart1_irq 14#define na_cpu ((void *) 0x00000000) // altera_nios2#define na_cpu_base 0x00000000#define na_timer1 ((np_timer *) 0x00000020) // altera_avalon_timer#define na_timer1_base 0x00000020#define na_timer1_irq 12#define na_uart2 ((np_uart *) 0x00000040) // altera_avalon_uart#define na_uart2_base 0x00000040#define na_uart2_irq 2#define na_led_pio ((np_pio *) 0x00000060) // altera_avalon_pio#define na_led_pio_base 0x00000060#define na_sysid ((void *) 0x00000070) // altera_avalon_sysid#define na_sysid_base 0x00000070#define na_sysid_end ((void *) 0x00000078)#define na_sysid_size 0x00000008#define na_jtag_uart ((void *) 0x00000078) // altera_avalon_jtag_uart#define na_jtag_uart_base 0x00000078#define na_jtag_uart_end ((void *) 0x00000080)#define na_jtag_uart_size 0x00000008#define na_jtag_uart_irq 10#define na_pll_0 ((void *) 0x00000080) // altera_avalon_pll#define na_pll_0_base 0x00000080#define na_pll_0_end ((void *) 0x000000a0)#define na_pll_0_size 0x00000020#define na_timer_dram ((np_timer *) 0x000000a0) // altera_avalon_timer#define na_timer_dram_base 0x000000a0#define na_timer_dram_irq 3#define na_cs8900_0 ((void *) 0x00000300) // altera_avalon_cs8900#define na_cs8900_0_base 0x00000300#define na_cs8900_0_end ((void *) 0x00000320)#define na_cs8900_0_size 0x00000020#define na_cs8900_0_irq 1#define na_idt7132 ((void *) 0x00000800) // altera_avalon_user_defined_interface#define na_idt7132_base 0x00000800#define na_idt7132_end ((void *) 0x00001000)#define na_idt7132_size 0x00000800#define na_onchip_rom ((void *) 0x00001000) // altera_avalon_onchip_memory#define na_onchip_rom_base 0x00001000#define na_onchip_rom_end ((void *) 0x00002000)#define na_onchip_rom_size 0x00001000#define na_epcs_controller ((np_epcs *) 0x00002000) // altera_avalon_epcs_flash_controller#define na_epcs_controller_base 0x00002000#define na_epcs_controller_irq 0#define na_cpu_jtag_debug_module ((void *) 0x00002800) // altera_nios2#define na_cpu_jtag_debug_module_base 0x00002800#define na_ext_ram ((void *) 0x00100000) // altera_nios_dev_kit_stratix_edition_sram2#define na_ext_ram_base 0x00100000#define na_ext_ram_end ((void *) 0x00200000)#define na_ext_ram_size 0x00100000#define na_cfi_flash_0 ((void *) 0x00200000) // altera_avalon_cfi_flash#define na_cfi_flash_0_base 0x00200000#define na_cfi_flash_0_end ((void *) 0x00400000)#define na_cfi_flash_0_size 0x00200000 #define na_null 0#define nasys_device_family "CYCLONE"#define nasys_epcs_count 1#define nasys_epcs_0 na_epcs_controller#define nasys_pio_count 1#define nasys_pio_0 na_led_pio#define nasys_timer_count 2#define nasys_timer_0 na_timer1#define nasys_timer_0_irq 12#define nasys_timer_1 na_timer_dram#define nasys_timer_1_irq 3#define nasys_uart_count 2#define nasys_uart_0 na_uart1#define nasys_uart_0_irq 14#define nasys_uart_1 na_uart2#define nasys_uart_1_irq 2#define nasys_reset_address ((void *) 0x00002000)#define nasys_exception_address ((void *) 0x00100020)#define nasys_break_address ((void *) 0x00002820)#define nasys_clock_freq 50000000#define nasys_clock_freq_1000 50000#define nasys_debug_core 0#define nasys_printf_uart na_uart1#define nasys_printf_uart_irq na_uart1_irq#define nm_printf_txchar nr_uart_txchar#define nm_printf_rxchar nr_uart_rxchar#define nasys_debug_uart na_uart1#define nasys_debug_uart_irq na_uart1_irq#define nasys_main_flash ((void *) 0x00002000)#define nasys_main_flash_size 0x00000800#define nasys_main_flash_end ((void *) 0x00002800)#define nasys_program_mem ((void *) 0x001000a0)#define nasys_program_mem_size 0x000fff60#define nasys_program_mem_end ((void *) 0x00200000)#define nasys_data_mem ((void *) 0x001000a0)#define nasys_data_mem_size 0x000fff60#define nasys_data_mem_end ((void *) 0x00200000)#define nasys_stack_top ((void *) 0x00200000) #define __nios_catch_irqs__ 1 // Include panic handler for all irqs (needs uart)#define __nios_use_constructors__ 1 // Call c++ static constructors#define __nios_use_small_printf__ 1 // Smaller non-ANSI printf, with no floating point#define nasys_has_icache 0 // True if instruction cache present#define nasys_icache_size 2048 // Size in bytes of instruction cache#define nasys_icache_line_size 32 // Size in bytes of each icache line#define nasys_icache_line_size_log2 5 // Log2 size in bytes of each icache line#define nasys_has_dcache 0 // True if instruction cache present#define nasys_dcache_size 1024 // Size in bytes of data cache#define nasys_dcache_line_size 4 // Size in bytes of each dcache line#define nasys_dcache_line_size_log2 2 // Log2 size in bytes of each dcache line#define PLUGS_PLUG_COUNT 5 // Maximum number of plugs#define PLUGS_ADAPTER_COUNT 2 // Maximum number of adapters#define PLUGS_DNS 1 // Have routines for DNS lookups#define PLUGS_PING 1 // Respond to icmp echo (ping) messages#define PLUGS_TCP 1 // Support tcp in/out connections#define PLUGS_IRQ 1 // Run at interrupte level#define PLUGS_DEBUG 1 // Support debug routines#define nm_system_name_string "fifth_nios2_system"#define nm_cpu_name_string "cpu"#define nm_monitor_string "design(5)"#define nm_cpu_architecture nios2#define nm_cpu_architecture_string "nios2"#define nios2 1// Structures and Routines For Each Peripheral
// Nios CPU Routines
void nr_zerorange(char *rangeStart,int rangeByteCount);
void nr_jumptoreset(void);
typedef void (*nios_callfromresetproc)(void);
void nr_callfromreset(nios_callfromresetproc procptr);
// Nios ISR Manager Routines
typedef void (*nios_isrhandlerproc)(int context);
typedef void (*nios_isrhandlerproc2)(int context,int irq_number,int interruptee_pc);
void nr_installuserisr(int trapNumber,nios_isrhandlerproc handlerProc,int context);
void nr_installuserisr2(int trapNumber,nios_isrhandlerproc2 handlerProc,int context);
// Nios GDB Stub Functions
void nios_gdb_install(int active);
#define nios_gdb_breakpoint() __asm__ volatile ("break")
// Nios OCI Defines
#define nios_oci_breakpoint() __asm__ volatile ("break")
// Default UART routines
void nr_txchar(int c);
void nr_txchar2(int c, int channel);
void nr_txstring(const char *s);
int nr_rxchar(void);
// Debug UART routines
void nr_debug_txchar(int c);
void nr_debug_txstring(const char *s);
int nr_debug_rxchar(void);
// Nios Private Printf Routines
int nr_printf(const char *fmt,...);
//int nr_fprintf( FILE *fp, const char *fmt, ... )
int nr_sprintf(char *sOut,const char *fmt,...);
#define nk_stdout 1
#define nk_stderr 2
#if (__nios_use_small_printf__ && !defined(__nios_use_large_printf))
#define printf nr_printf
#define fprintf nr_fprintf
#define sprintf nr_sprintf
#define setbuf(v1,v2) nr_setbuf(v1,v2) // does nothing
#endif
// Include nios cache-control definitions and macros
#include "nios_cache.h"
#include "nios2.h"
// UART Registerstypedef volatile struct { int np_uartrxdata; // Read-only, 8-bit int np_uarttxdata; // Write-only, 8-bit int np_uartstatus; // Read-only, 8-bit int np_uartcontrol; // Read/Write, 9-bit int np_uartdivisor; // Read/Write, 16-bit, optional int np_uartendofpacket; // Read/Write, end-of-packet character } np_uart;// UART Status Register Bitsenum { np_uartstatus_eop_bit = 12, np_uartstatus_cts_bit = 11, np_uartstatus_dcts_bit = 10, np_uartstatus_e_bit = 8, np_uartstatus_rrdy_bit = 7, np_uartstatus_trdy_bit = 6, np_uartstatus_tmt_bit = 5, np_uartstatus_toe_bit = 4, np_uartstatus_roe_bit = 3, np_uartstatus_brk_bit = 2, np_uartstatus_fe_bit = 1, np_uartstatus_pe_bit = 0, np_uartstatus_eop_mask = (1<<12), np_uartstatus_cts_mask = (1<<11), np_uartstatus_dcts_mask = (1<<10), np_uartstatus_e_mask = (1<<8), np_uartstatus_rrdy_mask = (1<<7), np_uartstatus_trdy_mask = (1<<6), np_uartstatus_tmt_mask = (1<<5), np_uartstatus_toe_mask = (1<<4), np_uartstatus_roe_mask = (1<<3), np_uartstatus_brk_mask = (1<<2), np_uartstatus_fe_mask = (1<<1), np_uartstatus_pe_mask = (1<<0) };// UART Control Register Bitsenum { np_uartcontrol_ieop_bit = 12, np_uartcontrol_rts_bit = 11, np_uartcontrol_idcts_bit = 10, np_uartcontrol_tbrk_bit = 9, np_uartcontrol_ie_bit = 8, np_uartcontrol_irrdy_bit = 7, np_uartcontrol_itrdy_bit = 6, np_uartcontrol_itmt_bit = 5, np_uartcontrol_itoe_bit = 4, np_uartcontrol_iroe_bit = 3, np_uartcontrol_ibrk_bit = 2, np_uartcontrol_ife_bit = 1, np_uartcontrol_ipe_bit = 0, np_uartcontrol_ieop_mask = (1<<12), np_uartcontrol_rts_mask = (1<<11), np_uartcontrol_idcts_mask = (1<<10), np_uartcontrol_tbrk_mask = (1<<9), np_uartcontrol_ie_mask = (1<<8), np_uartcontrol_irrdy_mask = (1<<7), np_uartcontrol_itrdy_mask = (1<<6), np_uartcontrol_itmt_mask = (1<<5), np_uartcontrol_itoe_mask = (1<<4), np_uartcontrol_iroe_mask = (1<<3), np_uartcontrol_ibrk_mask = (1<<2), np_uartcontrol_ife_mask = (1<<1), np_uartcontrol_ipe_mask = (1<<0) };// UART Routinesint nr_uart_rxchar(np_uart *uartBase); // 0 for default UARTvoid nr_uart_txcr(void);void nr_uart_txchar(int c,np_uart *uartBase); // 0 for default UARTvoid nr_uart_txhex(int x); // 16 or 32 bitsvoid nr_uart_txhex16(short x);void nr_uart_txhex32(long x);void nr_uart_txstring(char *s);// ----------------------------------------------// Timer Peripheral// Timer Registerstypedef volatile struct { int np_timerstatus; // read only, 2 bits (any write to clear TO) int np_timercontrol; // write/readable, 4 bits int np_timerperiodl; // write/readable, 16 bits int np_timerperiodh; // write/readable, 16 bits int np_timersnapl; // read only, 16 bits int np_timersnaph; // read only, 16 bits } np_timer;// Timer Register Bitsenum { np_timerstatus_run_bit = 1, // timer is running np_timerstatus_to_bit = 0, // timer has timed out np_timercontrol_stop_bit = 3, // stop the timer np_timercontrol_start_bit = 2, // start the timer np_timercontrol_cont_bit = 1, // continous mode np_timercontrol_ito_bit = 0, // enable time out interrupt np_timerstatus_run_mask = (1<<1), // timer is running np_timerstatus_to_mask = (1<<0), // timer has timed out np_timercontrol_stop_mask = (1<<3), // stop the timer np_timercontrol_start_mask = (1<<2), // start the timer np_timercontrol_cont_mask = (1<<1), // continous mode np_timercontrol_ito_mask = (1<<0) // enable time out interrupt };// Timer Routinesint nr_timer_milliseconds(void); // Starts on first call, hogs timer1.⌨️ 快捷键说明
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