asmdef.a

移植的S3C4510b的ucos-ii中的启动源代码

############Option##############
	###define _ISR_STARTADDRESS
#	.equ	_ISR_STARTADDRESS,		0x13FFF00 
	.equ	_ISR_STARTADDRESS,		0x0FFFF00 
	.equ	_PRIO_ISR_STARTADDR,	_ISR_STARTADDRESS+4*8


#########################################
# Define constant number used in program 
#########################################
	.equ	CPSR_DISABLE_INT,	0xC0		@	Disable all interrupts
	.equ	CPSR_MODE_MASK,		0x1F		@	Mode mask bits in CPSR

	.equ	CPSR_UDF_MODE,		0x1B		@	Undefined MODE
	.equ	CPSR_ABT_MODE,		0x17		@	Abort MODE
	.equ	CPSR_SUP_MODE,		0x13		@	Supervisal MODE
	.equ	CPSR_IRQ_MODE,		0x12		@	IRQ MODE
	.equ	CPSR_FIQ_MODE,		0x11	 	@	FIQ MODE
	.equ	CPSR_USR_MODE,		0x10		@	User MODE

	####special register bank base pointer
	.equ	SPREG_BASEADDR,		0x3FF0000
	
	####CLKCON
	.equ	CLKCON_ADDR,			SPREG_BASEADDR+0x3000
	
	####interrupt control registers
	.equ	INTMODE_ADDR,		SPREG_BASEADDR+0x4000
	.equ	INTPEND_ADDR,		SPREG_BASEADDR+0x4004
	.equ	INTMASK_ADDR,		SPREG_BASEADDR+0x4008
	
	.equ	INTPRI0_ADDR,		SPREG_BASEADDR+0x400C
	.equ	INTPRI1_ADDR,		SPREG_BASEADDR+0x4010
	.equ	INTPRI2_ADDR,		SPREG_BASEADDR+0x4014
	.equ	INTPRI3_ADDR,		SPREG_BASEADDR+0x4018
	.equ	INTPRI4_ADDR,		SPREG_BASEADDR+0x401C
	.equ	INTPRI5_ADDR,		SPREG_BASEADDR+0x4020
	
	.equ	INTOFFSET_ADDR,		SPREG_BASEADDR+0x4024
	.equ	INTPNDPRI_ADDR,		SPREG_BASEADDR+0x4028
	.equ	INTPNDTST_ADDR,		SPREG_BASEADDR+0x402C


	####exteral I/O registers
	.equ	EXTACON0_ADDR,		SPREG_BASEADDR+0x3008
	.equ	EXTACON1_ADDR,		SPREG_BASEADDR+0x300C
	
	####12 memory configure base address
	.equ	MEMCONFBASE_ADDR,	SPREG_BASEADDR+0x3010

##########ARM exception service routes address#############
	.equ	Reset_Handle,		_ISR_STARTADDRESS		
	.equ	ArmUndefHandle,		_ISR_STARTADDRESS+4		
	.equ	ArmSwiHandle,		_ISR_STARTADDRESS+4*2		
	.equ	ArmPreHandle,		_ISR_STARTADDRESS+4*3		
	.equ	ArmAbortHandle,		_ISR_STARTADDRESS+4*4		
	.equ	ArmRevHandle,		_ISR_STARTADDRESS+4*5		
	.equ	ArmIrqHandle,		_ISR_STARTADDRESS+4*6		
	.equ	ArmFiqHandle,		_ISR_STARTADDRESS+4*7		

############# ISR offset address related to prioty##############
	.equ	Handle_PRIOTY0,			_PRIO_ISR_STARTADDR 	
	.equ	Handle_PRIOTY1,			_PRIO_ISR_STARTADDR+4 	
	.equ	Handle_PRIOTY2,			_PRIO_ISR_STARTADDR+4*2 	
	.equ	Handle_PRIOTY3,			_PRIO_ISR_STARTADDR+4*3 	
	.equ	Handle_PRIOTY4,			_PRIO_ISR_STARTADDR+4*4 	
	.equ	Handle_PRIOTY5,			_PRIO_ISR_STARTADDR+4*5 	
	.equ	Handle_PRIOTY6,			_PRIO_ISR_STARTADDR+4*6 	
	.equ	Handle_PRIOTY7,			_PRIO_ISR_STARTADDR+4*7 	
	.equ	Handle_PRIOTY8,			_PRIO_ISR_STARTADDR+4*8 	
	.equ	Handle_PRIOTY9,			_PRIO_ISR_STARTADDR+4*9 	
	.equ	Handle_PRIOTY10,		_PRIO_ISR_STARTADDR+4*10 	
	.equ	Handle_PRIOTY11,		_PRIO_ISR_STARTADDR+4*11 	
	.equ	Handle_PRIOTY12,		_PRIO_ISR_STARTADDR+4*12 	
	.equ	Handle_PRIOTY13,		_PRIO_ISR_STARTADDR+4*13 	
	.equ	Handle_PRIOTY14,		_PRIO_ISR_STARTADDR+4*14 	
	.equ	Handle_PRIOTY15,		_PRIO_ISR_STARTADDR+4*15 	
	.equ	Handle_PRIOTY16,		_PRIO_ISR_STARTADDR+4*16 	
	.equ	Handle_PRIOTY17,		_PRIO_ISR_STARTADDR+4*17 	
	.equ	Handle_PRIOTY18,		_PRIO_ISR_STARTADDR+4*18 	
	.equ	Handle_PRIOTY19,		_PRIO_ISR_STARTADDR+4*19 	
	.equ	Handle_PRIOTY20,		_PRIO_ISR_STARTADDR+4*20