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移植的arm内核芯片 s3c4510 的ucos-ii的源码

	.GLOBAL ArmIRQIsr
#One of the following two routines can be used for non-vectored interrupt.
ArmIRQIsr:				/* using INTOFFSET register. */
    sub	    sp,sp,#4       	/* reserved for PC	  */
    stmfd   sp!,{r8-r10}   

	#IMPORTANT CAUTION
	#Reseted!INTOFFSET'value is 0x000054.
    ldr	    r8,=INTOFFSET_ADDR
    ldr	    r8,[r8]

	cmp		r8, #0x00054			/* If all interrupt pending bits are "0", 	*/
									/* r8 may be 0x00054 sometimes.			*/
	beq		HAVE_NOPENDING
HAVE_PENDING:
	#clear pend bit
	mov		r9, #0x1
	mov r8, r8, lsr #2
	mov r9, r9, lsl r8
	
	mov r8, r8, lsl #2
	
	LDR	r10, =INTPEND
	STR	r9, [r10]
	#interrupt bx
    ldr	    r9,=_PRIO_ISR_STARTADDR
    add	    r9,r9,r8
    ldr	    r9,[r9]
    str	    r9,[sp,#12]
    ldmfd   sp!,{r8-r10,pc}

HAVE_NOPENDING:
	ldmfd	sp!,{r8-r10}
	add		sp,sp,#4
	subs	pc,lr,#4