single_receive.vhd

来自「上海外滩看到的最大的LED显示屏的内核源代码」· VHDL 代码 · 共 62 行

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

ENTITY single_receive IS
PORT (	in_r        :IN		std_logic; 
		in_rclk		:IN		STD_LOGIC;
        out_r    	:OUT	std_logic;
        out_rclk  	:OUT	std_logic
		);

END single_receive;

ARCHITECTURE A OF single_receive IS 
  SIGNAL		rclk    	 : STD_LOGIC;
  SIGNAL		t0_in_r   	 : STD_LOGIC;
  SIGNAL		t1_in_r   	 : STD_LOGIC;

 BEGIN 
   out_rclk<=rclk;  
   rclk<=in_rclk;  
  -- process (in_rclk)
  --    begin
  --    if in_rclk'event and in_rclk='0' then
   --     rclk<=not rclk;
   --    end if;
  -- end process;

    process (rclk)
       begin
       if rclk'event and rclk='1' then
          t0_in_r<=in_r;
       end if;
   end process;

    process (rclk)
       begin
       if rclk'event and rclk='0' then
          t1_in_r<=in_r;
       end if;
   end process;

    process (rclk)
       begin
       if rclk'event and rclk='0' then
          if t0_in_r='0' and t1_in_r='1' then
             out_r<='0' ;
          elsif t0_in_r='1' and t1_in_r='0' then
             out_r<='1' ;
        --  else
        --     t0_in_r<=in_r;
          end if;
       end if;
   end process;

END ;