ldd_send.vhd

来自「上海外滩看到的最大的LED显示屏的内核源代码」· VHDL 代码 · 共 78 行

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

ENTITY ldd_send IS
PORT (	
        in_data   	:IN		STD_LOGIC;
        clk50M 	    :IN		STD_LOGIC;
        out_data   	:OUT	std_logic;
        out_clk  	:OUT	std_logic
		);

END ldd_send;

ARCHITECTURE A OF ldd_send IS 
 -- SIGNAL		send_counter : std_logic_vector(1 downto 0);
  SIGNAL		send_counter : std_logic;
  SIGNAL		ldd_clk    	 : STD_LOGIC;
  SIGNAL		rclk1    	 : STD_LOGIC;
  SIGNAL		rclk2    	 : STD_LOGIC;
  SIGNAL		rclk3    	 : STD_LOGIC;
  SIGNAL		rclk4    	 : STD_LOGIC;
  SIGNAL		rclk5    	 : STD_LOGIC;
  SIGNAL		rclk6    	 : STD_LOGIC;
  SIGNAL		rclk7    	 : STD_LOGIC;
  SIGNAL		data_temp   	 : STD_LOGIC;

 BEGIN 
 out_clk<=rclk1;
 out_data<=rclk1 when in_data='0' else
           rclk4   ; 
 process (clk50M)
       begin
       if clk50M'event and clk50M='1' then
          rclk1<=not rclk1; 
       end if;
   end process ;
 process (rclk1)
       begin
       if rclk1'event and rclk1='1' then
          rclk2<=not rclk2; 
       end if;
   end process ;
 process (rclk2)
       begin
       if rclk2'event and rclk2='1' then
          rclk3<=not rclk3; 
       end if;
   end process ;
 process (rclk3)
       begin
       if rclk3'event and rclk3='1' then
          rclk4<=not rclk4; 
       end if;
   end process ;

 process (rclk4)
       begin
       if rclk4'event and rclk4='1' then
          rclk5<=not rclk5; 
       end if;
   end process ;
 process (rclk5)
       begin
       if rclk5'event and rclk5='1' then
          rclk6<=not rclk6; 
       end if;
   end process ;
 process (rclk6)
       begin
       if rclk6'event and rclk6='1' then
          rclk7<=not rclk7; 
       end if;
   end process ;
END ;