📄 test_ldd.rpt
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| | | | +----------------------- LC31 |LDD_RECEIVE:2|count6
| | | | | +--------------------- LC20 |LDD_RECEIVE:2|count5
| | | | | | +------------------- LC19 |LDD_RECEIVE:2|count4
| | | | | | | +----------------- LC18 |LDD_RECEIVE:2|count3
| | | | | | | | +--------------- LC17 |LDD_RECEIVE:2|count2
| | | | | | | | | +------------- LC32 |LDD_RECEIVE:2|count1
| | | | | | | | | | +----------- LC28 |LDD_RECEIVE:2|count0
| | | | | | | | | | | +--------- LC27 |LDD_SEND:1|rclk1
| | | | | | | | | | | | +------- LC26 |LDD_SEND:1|rclk2
| | | | | | | | | | | | | +----- LC25 |LDD_SEND:1|rclk3
| | | | | | | | | | | | | | +--- LC24 |LDD_SEND:1|rclk4
| | | | | | | | | | | | | | | +- LC23 out_ldd
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC21 -> * - - - - - - - - - - - - - - * | - * | <-- |LDD_RECEIVE:2|count10
LC22 -> * * - - - - - - - - - - - - - * | - * | <-- |LDD_RECEIVE:2|count9
LC29 -> * * * - - - - - - - - - - - - * | - * | <-- |LDD_RECEIVE:2|count8
LC30 -> * * * * - - - - - - - - - - - * | - * | <-- |LDD_RECEIVE:2|count7
LC31 -> * * * * * - - - - - - - - - - * | - * | <-- |LDD_RECEIVE:2|count6
LC20 -> * * * * * * - - - - - - - - - * | - * | <-- |LDD_RECEIVE:2|count5
LC19 -> * * * * * * * - - - - - - - - * | - * | <-- |LDD_RECEIVE:2|count4
LC18 -> * * * * * * * * - - - - - - - * | - * | <-- |LDD_RECEIVE:2|count3
LC17 -> * * * * * * * * * - - - - - - * | - * | <-- |LDD_RECEIVE:2|count2
LC32 -> * * * * * * * * * * - - - - - * | - * | <-- |LDD_RECEIVE:2|count1
LC28 -> * * * * * * * * * * * - - - - * | - * | <-- |LDD_RECEIVE:2|count0
LC27 -> * * * * * * * * * * * * * - - * | - * | <-- |LDD_SEND:1|rclk1
LC26 -> - - - - - - - - - - - - * * - - | - * | <-- |LDD_SEND:1|rclk2
LC25 -> - - - - - - - - - - - - - * * - | - * | <-- |LDD_SEND:1|rclk3
LC24 -> * * * * * * * * * * * - - - * * | - * | <-- |LDD_SEND:1|rclk4
Pin
43 -> - - - - - - - - - - - - - - - - | - - | <-- clk50M
4 -> * * * * * * * * * * * - - - - * | - * | <-- ldd_data
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\cpld(huaqi)\test_ldd.rpt
test_ldd
** EQUATIONS **
clk50M : INPUT;
ldd_data : INPUT;
-- Node name is 'out_ldd' = '|LDD_RECEIVE:2|:3'
-- Equation name is 'out_ldd', type is output
out_ldd = DFFE( _EQ001 $ VCC, _EQ002, VCC, VCC, VCC);
_EQ001 = !_LC017 & !_LC018 & !_LC019 & !_LC020 & !_LC021 & !_LC022 &
!_LC029 & !_LC030 & !_LC031 & !_LC032
# !_LC017 & !_LC018 & !_LC019 & !_LC020 & !_LC021 & !_LC022 &
!_LC028 & !_LC029 & !_LC030 & !_LC031;
_EQ002 = _X001 & _X002;
_X001 = EXP( _LC027 & !ldd_data);
_X002 = EXP( _LC024 & ldd_data);
-- Node name is '|LDD_RECEIVE:2|:15' = '|LDD_RECEIVE:2|count0'
-- Equation name is '_LC028', type is buried
_LC028 = TFFE( VCC, _LC027, !_EQ003, VCC, VCC);
_EQ003 = _X001 & _X002;
_X001 = EXP( _LC027 & !ldd_data);
_X002 = EXP( _LC024 & ldd_data);
-- Node name is '|LDD_RECEIVE:2|:14' = '|LDD_RECEIVE:2|count1'
-- Equation name is '_LC032', type is buried
_LC032 = TFFE( _LC028, _LC027, !_EQ004, VCC, VCC);
_EQ004 = _X001 & _X002;
_X001 = EXP( _LC027 & !ldd_data);
_X002 = EXP( _LC024 & ldd_data);
-- Node name is '|LDD_RECEIVE:2|:13' = '|LDD_RECEIVE:2|count2'
-- Equation name is '_LC017', type is buried
_LC017 = TFFE( _EQ005, _LC027, !_EQ006, VCC, VCC);
_EQ005 = _LC028 & _LC032;
_EQ006 = _X001 & _X002;
_X001 = EXP( _LC027 & !ldd_data);
_X002 = EXP( _LC024 & ldd_data);
-- Node name is '|LDD_RECEIVE:2|:12' = '|LDD_RECEIVE:2|count3'
-- Equation name is '_LC018', type is buried
_LC018 = TFFE( _EQ007, _LC027, !_EQ008, VCC, VCC);
_EQ007 = _LC017 & _LC028 & _LC032;
_EQ008 = _X001 & _X002;
_X001 = EXP( _LC027 & !ldd_data);
_X002 = EXP( _LC024 & ldd_data);
-- Node name is '|LDD_RECEIVE:2|:11' = '|LDD_RECEIVE:2|count4'
-- Equation name is '_LC019', type is buried
_LC019 = TFFE( _EQ009, _LC027, !_EQ010, VCC, VCC);
_EQ009 = _LC017 & _LC018 & _LC028 & _LC032;
_EQ010 = _X001 & _X002;
_X001 = EXP( _LC027 & !ldd_data);
_X002 = EXP( _LC024 & ldd_data);
-- Node name is '|LDD_RECEIVE:2|:10' = '|LDD_RECEIVE:2|count5'
-- Equation name is '_LC020', type is buried
_LC020 = TFFE( _EQ011, _LC027, !_EQ012, VCC, VCC);
_EQ011 = _LC017 & _LC018 & _LC019 & _LC028 & _LC032;
_EQ012 = _X001 & _X002;
_X001 = EXP( _LC027 & !ldd_data);
_X002 = EXP( _LC024 & ldd_data);
-- Node name is '|LDD_RECEIVE:2|:9' = '|LDD_RECEIVE:2|count6'
-- Equation name is '_LC031', type is buried
_LC031 = TFFE( _EQ013, _LC027, !_EQ014, VCC, VCC);
_EQ013 = _LC017 & _LC018 & _LC019 & _LC020 & _LC028 & _LC032;
_EQ014 = _X001 & _X002;
_X001 = EXP( _LC027 & !ldd_data);
_X002 = EXP( _LC024 & ldd_data);
-- Node name is '|LDD_RECEIVE:2|:8' = '|LDD_RECEIVE:2|count7'
-- Equation name is '_LC030', type is buried
_LC030 = TFFE( _EQ015, _LC027, !_EQ016, VCC, VCC);
_EQ015 = _LC017 & _LC018 & _LC019 & _LC020 & _LC028 & _LC031 &
_LC032;
_EQ016 = _X001 & _X002;
_X001 = EXP( _LC027 & !ldd_data);
_X002 = EXP( _LC024 & ldd_data);
-- Node name is '|LDD_RECEIVE:2|:7' = '|LDD_RECEIVE:2|count8'
-- Equation name is '_LC029', type is buried
_LC029 = TFFE( _EQ017, _LC027, !_EQ018, VCC, VCC);
_EQ017 = _LC017 & _LC018 & _LC019 & _LC020 & _LC028 & _LC030 &
_LC031 & _LC032;
_EQ018 = _X001 & _X002;
_X001 = EXP( _LC027 & !ldd_data);
_X002 = EXP( _LC024 & ldd_data);
-- Node name is '|LDD_RECEIVE:2|:6' = '|LDD_RECEIVE:2|count9'
-- Equation name is '_LC022', type is buried
_LC022 = TFFE( _EQ019, _LC027, !_EQ020, VCC, VCC);
_EQ019 = _LC017 & _LC018 & _LC019 & _LC020 & _LC028 & _LC029 &
_LC030 & _LC031 & _LC032;
_EQ020 = _X001 & _X002;
_X001 = EXP( _LC027 & !ldd_data);
_X002 = EXP( _LC024 & ldd_data);
-- Node name is '|LDD_RECEIVE:2|:5' = '|LDD_RECEIVE:2|count10'
-- Equation name is '_LC021', type is buried
_LC021 = TFFE( _EQ021, _LC027, !_EQ022, VCC, VCC);
_EQ021 = _LC017 & _LC018 & _LC019 & _LC020 & _LC022 & _LC028 &
_LC029 & _LC030 & _LC031 & _LC032;
_EQ022 = _X001 & _X002;
_X001 = EXP( _LC027 & !ldd_data);
_X002 = EXP( _LC024 & ldd_data);
-- Node name is '|LDD_SEND:1|:5' = '|LDD_SEND:1|rclk1'
-- Equation name is '_LC027', type is buried
_LC027 = TFFE( VCC, GLOBAL( clk50M), VCC, VCC, VCC);
-- Node name is '|LDD_SEND:1|:6' = '|LDD_SEND:1|rclk2'
-- Equation name is '_LC026', type is buried
_LC026 = TFFE( VCC, _LC027, VCC, VCC, VCC);
-- Node name is '|LDD_SEND:1|:7' = '|LDD_SEND:1|rclk3'
-- Equation name is '_LC025', type is buried
_LC025 = TFFE( VCC, _LC026, VCC, VCC, VCC);
-- Node name is '|LDD_SEND:1|:8' = '|LDD_SEND:1|rclk4'
-- Equation name is '_LC024', type is buried
_LC024 = TFFE( VCC, _LC025, VCC, VCC, VCC);
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\cpld(huaqi)\test_ldd.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX3000A' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,435K
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