📄 ldd_receive.vhd
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY ldd_receive IS
PORT ( in_ldd :IN std_logic;
in_rclk :IN STD_LOGIC;
out_ldd :OUT std_logic
);
END ldd_receive;
ARCHITECTURE A OF ldd_receive IS
signal count : integer range 0 to 1024;
signal count1 : integer range 0 to 1024;
BEGIN
process(in_rclk)
begin
if in_ldd='0' then
count<=0;
elsif in_rclk='1' and in_rclk'event then
count<=count+1;
end if;
end process;
process(in_ldd)
begin
if in_ldd='0' and in_ldd'event then
if count<3 then
out_ldd<='0';
else
out_ldd<='1';
end if;
end if;
end process;
END ;
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