📄 ldd_receive.rpt
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(32) 25 B TFFE + t 0 0 0 0 4 1 6 count4 (:10)
(33) 24 B TFFE + t 0 0 0 0 3 1 7 count3 (:11)
(34) 23 B TFFE + t 0 0 0 0 2 1 8 count2 (:12)
- 22 B TFFE + t 0 0 0 0 1 1 9 count1 (:13)
(38) 20 B TFFE + t 0 0 0 0 0 0 10 count0 (:14)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\cpld(huaqi)\ldd_receive.rpt
ldd_receive
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----------------------- LC21 out_ldd
| +--------------------- LC26 count10
| | +------------------- LC27 count9
| | | +----------------- LC19 count8
| | | | +--------------- LC18 count7
| | | | | +------------- LC17 count6
| | | | | | +----------- LC28 count5
| | | | | | | +--------- LC25 count4
| | | | | | | | +------- LC24 count3
| | | | | | | | | +----- LC23 count2
| | | | | | | | | | +--- LC22 count1
| | | | | | | | | | | +- LC20 count0
| | | | | | | | | | | |
| | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC26 -> * * - - - - - - - - - - | - * | <-- count10
LC27 -> * * * - - - - - - - - - | - * | <-- count9
LC19 -> * * * * - - - - - - - - | - * | <-- count8
LC18 -> * * * * * - - - - - - - | - * | <-- count7
LC17 -> * * * * * * - - - - - - | - * | <-- count6
LC28 -> * * * * * * * - - - - - | - * | <-- count5
LC25 -> * * * * * * * * - - - - | - * | <-- count4
LC24 -> * * * * * * * * * - - - | - * | <-- count3
LC23 -> * * * * * * * * * * - - | - * | <-- count2
LC22 -> * * * * * * * * * * * - | - * | <-- count1
LC20 -> - * * * * * * * * * * * | - * | <-- count0
Pin
1 -> - - - - - - - - - - - - | - - | <-- in_ldd
43 -> - - - - - - - - - - - - | - - | <-- in_rclk
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\cpld(huaqi)\ldd_receive.rpt
ldd_receive
** EQUATIONS **
in_ldd : INPUT;
in_rclk : INPUT;
-- Node name is ':14' = 'count0'
-- Equation name is 'count0', location is LC020, type is buried.
count0 = TFFE( VCC, GLOBAL( in_rclk), GLOBAL( in_ldd), VCC, VCC);
-- Node name is ':13' = 'count1'
-- Equation name is 'count1', location is LC022, type is buried.
count1 = TFFE( count0, GLOBAL( in_rclk), GLOBAL( in_ldd), VCC, VCC);
-- Node name is ':12' = 'count2'
-- Equation name is 'count2', location is LC023, type is buried.
count2 = TFFE( _EQ001, GLOBAL( in_rclk), GLOBAL( in_ldd), VCC, VCC);
_EQ001 = count0 & count1;
-- Node name is ':11' = 'count3'
-- Equation name is 'count3', location is LC024, type is buried.
count3 = TFFE( _EQ002, GLOBAL( in_rclk), GLOBAL( in_ldd), VCC, VCC);
_EQ002 = count0 & count1 & count2;
-- Node name is ':10' = 'count4'
-- Equation name is 'count4', location is LC025, type is buried.
count4 = TFFE( _EQ003, GLOBAL( in_rclk), GLOBAL( in_ldd), VCC, VCC);
_EQ003 = count0 & count1 & count2 & count3;
-- Node name is ':9' = 'count5'
-- Equation name is 'count5', location is LC028, type is buried.
count5 = TFFE( _EQ004, GLOBAL( in_rclk), GLOBAL( in_ldd), VCC, VCC);
_EQ004 = count0 & count1 & count2 & count3 & count4;
-- Node name is ':8' = 'count6'
-- Equation name is 'count6', location is LC017, type is buried.
count6 = TFFE( _EQ005, GLOBAL( in_rclk), GLOBAL( in_ldd), VCC, VCC);
_EQ005 = count0 & count1 & count2 & count3 & count4 & count5;
-- Node name is ':7' = 'count7'
-- Equation name is 'count7', location is LC018, type is buried.
count7 = TFFE( _EQ006, GLOBAL( in_rclk), GLOBAL( in_ldd), VCC, VCC);
_EQ006 = count0 & count1 & count2 & count3 & count4 & count5 &
count6;
-- Node name is ':6' = 'count8'
-- Equation name is 'count8', location is LC019, type is buried.
count8 = TFFE( _EQ007, GLOBAL( in_rclk), GLOBAL( in_ldd), VCC, VCC);
_EQ007 = count0 & count1 & count2 & count3 & count4 & count5 &
count6 & count7;
-- Node name is ':5' = 'count9'
-- Equation name is 'count9', location is LC027, type is buried.
count9 = TFFE( _EQ008, GLOBAL( in_rclk), GLOBAL( in_ldd), VCC, VCC);
_EQ008 = count0 & count1 & count2 & count3 & count4 & count5 &
count6 & count7 & count8;
-- Node name is ':4' = 'count10'
-- Equation name is 'count10', location is LC026, type is buried.
count10 = TFFE( _EQ009, GLOBAL( in_rclk), GLOBAL( in_ldd), VCC, VCC);
_EQ009 = count0 & count1 & count2 & count3 & count4 & count5 &
count6 & count7 & count8 & count9;
-- Node name is 'out_ldd'
-- Equation name is 'out_ldd', location is LC021, type is output.
out_ldd = LCELL( _EQ010 $ VCC);
_EQ010 = !count1 & !count2 & !count3 & !count4 & !count5 & !count6 &
!count7 & !count8 & !count9 & !count10;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\cpld(huaqi)\ldd_receive.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX3000A' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,666K
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