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Device-Specific Information: d:\cpld(huaqi)\encode.rpt
encode
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+------------------- LC46 out_g
| +----------------- LC37 out_r
| | +--------------- LC33 out_rclk
| | | +------------- LC43 |SINGLE_SEND:1|send_counter
| | | | +----------- LC42 |SINGLE_SEND:1|data_temp
| | | | | +--------- LC41 |SINGLE_SEND:12|send_counter
| | | | | | +------- LC40 |SINGLE_SEND:12|data_temp
| | | | | | | +----- LC36 |SINGLE_SEND:23|send_counter
| | | | | | | | +--- LC35 |SINGLE_SEND:24|send_counter
| | | | | | | | | +- LC34 |SINGLE_SEND:35|send_counter
| | | | | | | | | |
| | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
LC43 -> - * - * * - - - - - | - - * - | <-- |SINGLE_SEND:1|send_counter
LC42 -> - * - - * - - - - - | - - * - | <-- |SINGLE_SEND:1|data_temp
LC41 -> * - - - - * * - - - | - - * - | <-- |SINGLE_SEND:12|send_counter
LC40 -> * - - - - - * - - - | - - * - | <-- |SINGLE_SEND:12|data_temp
Pin
9 -> - - - - - - * - - - | - - * - | <-- g_data
16 -> * * * * * * * * * * | - - * * | <-- in_clk
8 -> - - - - * - - - - - | - - * - | <-- r_data
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\cpld(huaqi)\encode.rpt
encode
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+----------- LC49 out_b
| +--------- LC53 out_lat
| | +------- LC51 out_oe
| | | +----- LC54 |SINGLE_SEND:23|data_temp
| | | | +--- LC52 |SINGLE_SEND:24|data_temp
| | | | | +- LC50 |SINGLE_SEND:35|data_temp
| | | | | |
| | | | | | Other LABs fed by signals
| | | | | | that feed LAB 'D'
LC | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC54 -> * - - * - - | - - - * | <-- |SINGLE_SEND:23|data_temp
LC52 -> - - * - * - | - - - * | <-- |SINGLE_SEND:24|data_temp
LC50 -> - * - - - * | - - - * | <-- |SINGLE_SEND:35|data_temp
Pin
11 -> - - - * - - | - - - * | <-- b_data
16 -> * * * * * * | - - * * | <-- in_clk
14 -> - - - - - * | - - - * | <-- lat_data
12 -> - - - - * - | - - - * | <-- oe_data
LC36 -> * - - * - - | - - - * | <-- |SINGLE_SEND:23|send_counter
LC35 -> - - * - * - | - - - * | <-- |SINGLE_SEND:24|send_counter
LC34 -> - * - - - * | - - - * | <-- |SINGLE_SEND:35|send_counter
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\cpld(huaqi)\encode.rpt
encode
** EQUATIONS **
b_data : INPUT;
g_data : INPUT;
in_clk : INPUT;
lat_data : INPUT;
oe_data : INPUT;
r_data : INPUT;
-- Node name is 'out_b' = '|SINGLE_SEND:23|:3'
-- Equation name is 'out_b', type is output
out_b = DFFE( _LC036 $ _LC054, in_clk, VCC, VCC, VCC);
-- Node name is 'out_g' = '|SINGLE_SEND:12|:3'
-- Equation name is 'out_g', type is output
out_g = DFFE( _LC041 $ _LC040, in_clk, VCC, VCC, VCC);
-- Node name is 'out_lat' = '|SINGLE_SEND:35|:3'
-- Equation name is 'out_lat', type is output
out_lat = DFFE( _LC034 $ _LC050, in_clk, VCC, VCC, VCC);
-- Node name is 'out_oe' = '|SINGLE_SEND:24|:3'
-- Equation name is 'out_oe', type is output
out_oe = DFFE( _LC035 $ _LC052, in_clk, VCC, VCC, VCC);
-- Node name is 'out_r' = '|SINGLE_SEND:1|:3'
-- Equation name is 'out_r', type is output
out_r = DFFE( _LC043 $ _LC042, in_clk, VCC, VCC, VCC);
-- Node name is 'out_rclk'
-- Equation name is 'out_rclk', location is LC033, type is output.
out_rclk = LCELL( in_clk $ GND);
-- Node name is '|SINGLE_SEND:1|:7' = '|SINGLE_SEND:1|data_temp'
-- Equation name is '_LC042', type is buried
_LC042 = DFFE( _EQ001 $ GND, in_clk, VCC, VCC, VCC);
_EQ001 = _LC042 & _LC043
# !_LC043 & r_data;
-- Node name is '|SINGLE_SEND:1|:6' = '|SINGLE_SEND:1|send_counter'
-- Equation name is '_LC043', type is buried
_LC043 = TFFE( VCC, in_clk, VCC, VCC, VCC);
-- Node name is '|SINGLE_SEND:12|:7' = '|SINGLE_SEND:12|data_temp'
-- Equation name is '_LC040', type is buried
_LC040 = DFFE( _EQ002 $ GND, in_clk, VCC, VCC, VCC);
_EQ002 = _LC040 & _LC041
# g_data & !_LC041;
-- Node name is '|SINGLE_SEND:12|:6' = '|SINGLE_SEND:12|send_counter'
-- Equation name is '_LC041', type is buried
_LC041 = TFFE( VCC, in_clk, VCC, VCC, VCC);
-- Node name is '|SINGLE_SEND:23|:7' = '|SINGLE_SEND:23|data_temp'
-- Equation name is '_LC054', type is buried
_LC054 = DFFE( _EQ003 $ GND, in_clk, VCC, VCC, VCC);
_EQ003 = _LC036 & _LC054
# b_data & !_LC036;
-- Node name is '|SINGLE_SEND:23|:6' = '|SINGLE_SEND:23|send_counter'
-- Equation name is '_LC036', type is buried
_LC036 = TFFE( VCC, in_clk, VCC, VCC, VCC);
-- Node name is '|SINGLE_SEND:24|:7' = '|SINGLE_SEND:24|data_temp'
-- Equation name is '_LC052', type is buried
_LC052 = DFFE( _EQ004 $ GND, in_clk, VCC, VCC, VCC);
_EQ004 = _LC035 & _LC052
# !_LC035 & oe_data;
-- Node name is '|SINGLE_SEND:24|:6' = '|SINGLE_SEND:24|send_counter'
-- Equation name is '_LC035', type is buried
_LC035 = TFFE( VCC, in_clk, VCC, VCC, VCC);
-- Node name is '|SINGLE_SEND:35|:7' = '|SINGLE_SEND:35|data_temp'
-- Equation name is '_LC050', type is buried
_LC050 = DFFE( _EQ005 $ GND, in_clk, VCC, VCC, VCC);
_EQ005 = _LC034 & _LC050
# lat_data & !_LC034;
-- Node name is '|SINGLE_SEND:35|:6' = '|SINGLE_SEND:35|send_counter'
-- Equation name is '_LC034', type is buried
_LC034 = TFFE( VCC, in_clk, VCC, VCC, VCC);
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\cpld(huaqi)\encode.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX3000A' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = off
Automatic Global Clear = off
Automatic Global Preset = off
Automatic Global Output Enable = off
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,390K
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