📄 decode.rpt
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| | +----------- LC46 out_g
| | | +--------- LC41 out_r
| | | | +------- LC48 |SINGLE_RECEIVE:57|t0_in_r
| | | | | +----- LC44 |SINGLE_RECEIVE:57|t1_in_r
| | | | | | +--- LC42 |SINGLE_RECEIVE:58|t0_in_r
| | | | | | | +- LC36 |SINGLE_RECEIVE:58|t1_in_r
| | | | | | | |
| | | | | | | | Other LABs fed by signals
| | | | | | | | that feed LAB 'C'
LC | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
LC33 -> * * - - - - - - | - - * - | <-- |LDD_SEND:45|rclk3
LC46 -> - - * - - - - - | - - * - | <-- out_g
LC41 -> - - - * - - - - | - - * - | <-- out_r
Pin
11 -> - - - - * * - - | - - * - | <-- b_data
43 -> - - - - - - - - | * - - - | <-- clk50M
12 -> - - - - - - * * | - - * - | <-- oe_data
LC2 -> * - - - - - - - | - - * - | <-- |LDD_SEND:45|rclk2
LC57 -> - - * * * * * * | - - * * | <-- out_rclk
LC61 -> - - - * - - - - | - - * - | <-- |SINGLE_RECEIVE:55|t0_in_r
LC59 -> - - - * - - - - | - - * - | <-- |SINGLE_RECEIVE:55|t1_in_r
LC58 -> - - * - - - - - | - - * - | <-- |SINGLE_RECEIVE:56|t0_in_r
LC56 -> - - * - - - - - | - - * - | <-- |SINGLE_RECEIVE:56|t1_in_r
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\ljc\cpld(huaqi)\decode.rpt
decode
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------------------------------- LC50 |LAT_RECEIVE:46|LPM_ADD_SUB:488|addcore:adder|addcore:adder0|result_node1
| +----------------------------- LC52 |LAT_RECEIVE:46|LPM_ADD_SUB:488|addcore:adder|addcore:adder0|result_node2
| | +--------------------------- LC54 |LAT_RECEIVE:46|count3
| | | +------------------------- LC60 |LAT_RECEIVE:46|count2
| | | | +----------------------- LC64 |LAT_RECEIVE:46|count1
| | | | | +--------------------- LC63 |LAT_RECEIVE:46|count0
| | | | | | +------------------- LC62 |LAT_RECEIVE:46|t0_in_lat
| | | | | | | +----------------- LC55 |LAT_RECEIVE:46|t1_in_lat
| | | | | | | | +--------------- LC49 out_b
| | | | | | | | | +------------- LC51 out_lat
| | | | | | | | | | +----------- LC53 out_oe
| | | | | | | | | | | +--------- LC57 out_rclk
| | | | | | | | | | | | +------- LC61 |SINGLE_RECEIVE:55|t0_in_r
| | | | | | | | | | | | | +----- LC59 |SINGLE_RECEIVE:55|t1_in_r
| | | | | | | | | | | | | | +--- LC58 |SINGLE_RECEIVE:56|t0_in_r
| | | | | | | | | | | | | | | +- LC56 |SINGLE_RECEIVE:56|t1_in_r
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC50 -> - - - - * - - - - - - - - - - - | - - - * | <-- |LAT_RECEIVE:46|LPM_ADD_SUB:488|addcore:adder|addcore:adder0|result_node1
LC52 -> - - - * - - - - - - - - - - - - | - - - * | <-- |LAT_RECEIVE:46|LPM_ADD_SUB:488|addcore:adder|addcore:adder0|result_node2
LC54 -> - - * * * * - - - - - * - - - - | - - - * | <-- |LAT_RECEIVE:46|count3
LC60 -> - * * * * * - - - - - * - - - - | - - - * | <-- |LAT_RECEIVE:46|count2
LC64 -> * * * - - - - - - - - * - - - - | - - - * | <-- |LAT_RECEIVE:46|count1
LC63 -> * * * - - * - - - - - * - - - - | - - - * | <-- |LAT_RECEIVE:46|count0
LC62 -> - - - - - - - - - * - - - - - - | - - - * | <-- |LAT_RECEIVE:46|t0_in_lat
LC55 -> - - - - - - - - - * - - - - - - | - - - * | <-- |LAT_RECEIVE:46|t1_in_lat
LC49 -> - - - - - - - - * - - - - - - - | - - - * | <-- out_b
LC51 -> - - * * * * - - - * - - - - - - | - - - * | <-- out_lat
LC53 -> - - - - - - - - - - * - - - - - | - - - * | <-- out_oe
LC57 -> - - - - - - * * * * * * * * * * | - - * * | <-- out_rclk
Pin
43 -> - - - - - - - - - - - - - - - - | * - - - | <-- clk50M
9 -> - - - - - - - - - - - - - - * * | - - - * | <-- g_data
14 -> - - - - - - * * - - - - - - - - | - - - * | <-- lat_data
16 -> - - * * * * - - - - - * - - - - | - - - * | <-- rclk
8 -> - - - - - - - - - - - - * * - - | - - - * | <-- r_data
LC48 -> - - - - - - - - * - - - - - - - | - - - * | <-- |SINGLE_RECEIVE:57|t0_in_r
LC44 -> - - - - - - - - * - - - - - - - | - - - * | <-- |SINGLE_RECEIVE:57|t1_in_r
LC42 -> - - - - - - - - - - * - - - - - | - - - * | <-- |SINGLE_RECEIVE:58|t0_in_r
LC36 -> - - - - - - - - - - * - - - - - | - - - * | <-- |SINGLE_RECEIVE:58|t1_in_r
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\ljc\cpld(huaqi)\decode.rpt
decode
** EQUATIONS **
b_data : INPUT;
clk50M : INPUT;
g_data : INPUT;
lat_data : INPUT;
ldd_data : INPUT;
oe_data : INPUT;
rclk : INPUT;
r_data : INPUT;
-- Node name is 'clk_ldd' = '|LDD_SEND:45|rclk1'
-- Equation name is 'clk_ldd', type is output
clk_ldd = TFFE( VCC, clk50M, VCC, VCC, VCC);
-- Node name is 'out_b' = '|SINGLE_RECEIVE:57|:3'
-- Equation name is 'out_b', type is output
out_b = DFFE( _EQ001 $ _LC048, !out_rclk, VCC, VCC, VCC);
_EQ001 = _LC044 & _LC048 & !out_b
# !_LC044 & !_LC048 & out_b;
-- Node name is 'out_g' = '|SINGLE_RECEIVE:56|:3'
-- Equation name is 'out_g', type is output
out_g = DFFE( _EQ002 $ _LC058, !out_rclk, VCC, VCC, VCC);
_EQ002 = _LC056 & _LC058 & !out_g
# !_LC056 & !_LC058 & out_g;
-- Node name is 'out_lat' = '|LAT_RECEIVE:46|lat_temp'
-- Equation name is 'out_lat', type is output
out_lat = DFFE( _EQ003 $ _LC062, !out_rclk, VCC, VCC, VCC);
_EQ003 = _LC055 & _LC062 & !out_lat
# !_LC055 & !_LC062 & out_lat;
-- Node name is 'out_ldd'
-- Equation name is 'out_ldd', location is LC011, type is output.
out_ldd = LCELL( _EQ004 $ GND);
_EQ004 = _LC034 & ldd_data
# clk_ldd & !ldd_data;
-- Node name is 'out_oe' = '|SINGLE_RECEIVE:58|:3'
-- Equation name is 'out_oe', type is output
out_oe = DFFE( _EQ005 $ _LC042, !out_rclk, VCC, VCC, VCC);
_EQ005 = _LC036 & _LC042 & !out_oe
# !_LC036 & !_LC042 & out_oe;
-- Node name is 'out_r' = '|SINGLE_RECEIVE:55|:3'
-- Equation name is 'out_r', type is output
out_r = DFFE( _EQ006 $ _LC061, !out_rclk, VCC, VCC, VCC);
_EQ006 = _LC059 & _LC061 & !out_r
# !_LC059 & !_LC061 & out_r;
-- Node name is 'out_rclk' = '|LAT_RECEIVE:46|rclk'
-- Equation name is 'out_rclk', type is output
out_rclk = DFFE( _EQ007 $ _EQ008, !rclk, VCC, VCC, VCC);
_EQ007 = _LC054 & _LC060 & _LC063 & !out_rclk
# _LC054 & _LC064 & !out_rclk & _X001;
_X001 = EXP(!_LC060 & !_LC063);
_EQ008 = _X002 & _X003 & _X004 & _X005;
_X002 = EXP(!_LC060 & !_LC064 & out_rclk);
_X003 = EXP(!_LC060 & !_LC063 & out_rclk);
_X004 = EXP(!_LC063 & !_LC064 & out_rclk);
_X005 = EXP(!_LC054 & out_rclk);
-- Node name is '|LAT_RECEIVE:46|:15' = '|LAT_RECEIVE:46|count0'
-- Equation name is '_LC063', type is buried
_LC063 = DFFE( _EQ009 $ GND, rclk, out_lat, VCC, VCC);
_EQ009 = _LC054 & !_LC060 & !_LC063
# !_LC054 & !_LC063;
-- Node name is '|LAT_RECEIVE:46|:14' = '|LAT_RECEIVE:46|count1'
-- Equation name is '_LC064', type is buried
_LC064 = DFFE( _EQ010 $ GND, rclk, out_lat, VCC, VCC);
_EQ010 = _LC050 & _LC054 & !_LC060
# _LC050 & !_LC054;
-- Node name is '|LAT_RECEIVE:46|:13' = '|LAT_RECEIVE:46|count2'
-- Equation name is '_LC060', type is buried
_LC060 = DFFE( _EQ011 $ GND, rclk, out_lat, VCC, VCC);
_EQ011 = _LC052 & _LC054 & !_LC060
# _LC052 & !_LC054;
-- Node name is '|LAT_RECEIVE:46|:12' = '|LAT_RECEIVE:46|count3'
-- Equation name is '_LC054', type is buried
_LC054 = DFFE( _EQ012 $ GND, rclk, out_lat, VCC, VCC);
_EQ012 = !_LC054 & _LC060 & _LC063 & _LC064
# _LC054 & !_LC060 & _X006;
_X006 = EXP( _LC060 & _LC063 & _LC064);
-- Node name is '|LAT_RECEIVE:46|LPM_ADD_SUB:488|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC050', type is buried
_LC050 = LCELL( _LC064 $ _LC063);
-- Node name is '|LAT_RECEIVE:46|LPM_ADD_SUB:488|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC052', type is buried
_LC052 = LCELL( _LC060 $ _EQ013);
_EQ013 = _LC063 & _LC064;
-- Node name is '|LAT_RECEIVE:46|:17' = '|LAT_RECEIVE:46|t0_in_lat'
-- Equation name is '_LC062', type is buried
_LC062 = DFFE( lat_data $ GND, out_rclk, VCC, VCC, VCC);
-- Node name is '|LAT_RECEIVE:46|:18' = '|LAT_RECEIVE:46|t1_in_lat'
-- Equation name is '_LC055', type is buried
_LC055 = DFFE( lat_data $ GND, !out_rclk, VCC, VCC, VCC);
-- Node name is '|LDD_SEND:45|:6' = '|LDD_SEND:45|rclk2'
-- Equation name is '_LC002', type is buried
_LC002 = TFFE( VCC, clk_ldd, VCC, VCC, VCC);
-- Node name is '|LDD_SEND:45|:7' = '|LDD_SEND:45|rclk3'
-- Equation name is '_LC033', type is buried
_LC033 = TFFE( VCC, _LC002, VCC, VCC, VCC);
-- Node name is '|LDD_SEND:45|:8' = '|LDD_SEND:45|rclk4'
-- Equation name is '_LC034', type is buried
_LC034 = TFFE( VCC, _LC033, VCC, VCC, VCC);
-- Node name is '|SINGLE_RECEIVE:55|:7' = '|SINGLE_RECEIVE:55|t0_in_r'
-- Equation name is '_LC061', type is buried
_LC061 = DFFE( r_data $ GND, out_rclk, VCC, VCC, VCC);
-- Node name is '|SINGLE_RECEIVE:55|:8' = '|SINGLE_RECEIVE:55|t1_in_r'
-- Equation name is '_LC059', type is buried
_LC059 = DFFE( r_data $ GND, !out_rclk, VCC, VCC, VCC);
-- Node name is '|SINGLE_RECEIVE:56|:7' = '|SINGLE_RECEIVE:56|t0_in_r'
-- Equation name is '_LC058', type is buried
_LC058 = DFFE( g_data $ GND, out_rclk, VCC, VCC, VCC);
-- Node name is '|SINGLE_RECEIVE:56|:8' = '|SINGLE_RECEIVE:56|t1_in_r'
-- Equation name is '_LC056', type is buried
_LC056 = DFFE( g_data $ GND, !out_rclk, VCC, VCC, VCC);
-- Node name is '|SINGLE_RECEIVE:57|:7' = '|SINGLE_RECEIVE:57|t0_in_r'
-- Equation name is '_LC048', type is buried
_LC048 = DFFE( b_data $ GND, out_rclk, VCC, VCC, VCC);
-- Node name is '|SINGLE_RECEIVE:57|:8' = '|SINGLE_RECEIVE:57|t1_in_r'
-- Equation name is '_LC044', type is buried
_LC044 = DFFE( b_data $ GND, !out_rclk, VCC, VCC, VCC);
-- Node name is '|SINGLE_RECEIVE:58|:7' = '|SINGLE_RECEIVE:58|t0_in_r'
-- Equation name is '_LC042', type is buried
_LC042 = DFFE( oe_data $ GND, out_rclk, VCC, VCC, VCC);
-- Node name is '|SINGLE_RECEIVE:58|:8' = '|SINGLE_RECEIVE:58|t1_in_r'
-- Equation name is '_LC036', type is buried
_LC036 = DFFE( oe_data $ GND, !out_rclk, VCC, VCC, VCC);
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\ljc\cpld(huaqi)\decode.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX3000A' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = off
Automatic Global Clear = off
Automatic Global Preset = off
Automatic Global Output Enable = off
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:01
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,483K
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