📄 decode.rpt
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Project Information e:\ljc\cpld(huaqi)\decode.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 11/25/2004 16:43:09
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
decode EPM3064ALC44-10 8 8 0 27 6 42 %
User Pins: 8 8 0
Project Information e:\ljc\cpld(huaqi)\decode.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Flipflop '|LAT_RECEIVE:46|:5' stuck at GND
Warning: Flipflop '|LAT_RECEIVE:46|:6' stuck at GND
Warning: Flipflop '|LAT_RECEIVE:46|:7' stuck at GND
Warning: Flipflop '|LAT_RECEIVE:46|:11' stuck at GND
Warning: Flipflop '|LAT_RECEIVE:46|:8' stuck at GND
Warning: Flipflop '|LAT_RECEIVE:46|:9' stuck at GND
Warning: Flipflop '|LAT_RECEIVE:46|:10' stuck at GND
Project Information e:\ljc\cpld(huaqi)\decode.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
decode@11 b_data
decode@5 clk_ldd
decode@43 clk50M
decode@9 g_data
decode@14 lat_data
decode@4 ldd_data
decode@12 oe_data
decode@33 out_b
decode@31 out_g
decode@34 out_lat
decode@6 out_ldd
decode@37 out_oe
decode@29 out_r
decode@39 out_rclk
decode@16 rclk
decode@8 r_data
Project Information e:\ljc\cpld(huaqi)\decode.rpt
** FILE HIERARCHY **
|single_receive:55|
|single_receive:56|
|single_receive:57|
|single_receive:58|
|lat_receive:46|
|lat_receive:46|lpm_add_sub:488|
|lat_receive:46|lpm_add_sub:488|addcore:adder|
|lat_receive:46|lpm_add_sub:488|addcore:adder|addcore:adder1|
|lat_receive:46|lpm_add_sub:488|addcore:adder|addcore:adder0|
|lat_receive:46|lpm_add_sub:488|altshift:result_ext_latency_ffs|
|lat_receive:46|lpm_add_sub:488|altshift:carry_ext_latency_ffs|
|lat_receive:46|lpm_add_sub:488|altshift:oflow_ext_latency_ffs|
|ldd_send:45|
Device-Specific Information: e:\ljc\cpld(huaqi)\decode.rpt
decode
***** Logic for device 'decode' compiled without errors.
Device: EPM3064ALC44-10
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffffffff
MultiVolt I/O = OFF
l R R
o c d E E
u l d V c S S
t k _ C l E E
_ _ d C k R R
l l a I G G G 5 G V V
d d t N N N N 0 N E E
d d a T D D D M D D D
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
#TDI | 7 39 | out_rclk
r_data | 8 38 | #TDO
g_data | 9 37 | out_oe
GND | 10 36 | GND
b_data | 11 35 | VCCIO
oe_data | 12 EPM3064ALC44-10 34 | out_lat
#TMS | 13 33 | out_b
lat_data | 14 32 | #TCK
VCCIO | 15 31 | out_g
rclk | 16 30 | GND
GND | 17 29 | out_r
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
R R R R G V R R R R R
E E E E N C E E E E E
S S S S D C S S S S S
E E E E I E E E E E
R R R R N R R R R R
V V V V T V V V V V
E E E E E E E E E
D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: e:\ljc\cpld(huaqi)\decode.rpt
decode
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 3/16( 18%) 8/ 8(100%) 0/16( 0%) 4/36( 11%)
B: LC17 - LC32 0/16( 0%) 3/ 7( 42%) 0/16( 0%) 0/36( 0%)
C: LC33 - LC48 8/16( 50%) 3/ 8( 37%) 0/16( 0%) 11/36( 30%)
D: LC49 - LC64 16/16(100%) 5/ 7( 71%) 6/16( 37%) 20/36( 55%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 19/30 ( 63%)
Total logic cells used: 27/64 ( 42%)
Total shareable expanders used: 6/64 ( 9%)
Total Turbo logic cells used: 27/64 ( 42%)
Total shareable expanders not available (n/a): 0/64 ( 0%)
Average fan-in: 3.07
Total fan-in: 83
Total input pins required: 8
Total output pins required: 8
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 27
Total flipflops required: 24
Total product terms required: 80
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 6
Synthesized logic cells: 0/ 64 ( 0%)
Device-Specific Information: e:\ljc\cpld(huaqi)\decode.rpt
decode
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
11 (3) (A) INPUT 0 0 0 0 0 0 2 b_data
43 - - INPUT 0 0 0 0 0 1 0 clk50M
9 (4) (A) INPUT 0 0 0 0 0 0 2 g_data
14 (30) (B) INPUT 0 0 0 0 0 0 2 lat_data
4 (16) (A) INPUT 0 0 0 0 0 1 0 ldd_data
12 (1) (A) INPUT 0 0 0 0 0 0 2 oe_data
16 (25) (B) INPUT 0 0 0 0 0 1 4 rclk
8 (5) (A) INPUT 0 0 0 0 0 0 2 r_data
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\ljc\cpld(huaqi)\decode.rpt
decode
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
5 14 A FF t 0 0 0 1 0 1 1 clk_ldd (|LDD_SEND:45|:5)
33 49 D FF t 0 0 0 0 4 1 0 out_b
31 46 C FF t 0 0 0 0 4 1 0 out_g
34 51 D FF t 0 0 0 0 4 1 4 out_lat (|LAT_RECEIVE:46|:19)
6 11 A OUTPUT t 0 0 0 1 2 0 0 out_ldd
37 53 D FF t 0 0 0 0 4 1 0 out_oe
29 41 C FF t 0 0 0 0 4 1 0 out_r
39 57 D FF t 5 0 0 1 5 6 10 out_rclk (|LAT_RECEIVE:46|:16)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\ljc\cpld(huaqi)\decode.rpt
decode
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 50 D SOFT t 0 0 0 0 2 0 1 |LAT_RECEIVE:46|LPM_ADD_SUB:488|addcore:adder|addcore:adder0|result_node1
- 52 D SOFT t 0 0 0 0 3 0 1 |LAT_RECEIVE:46|LPM_ADD_SUB:488|addcore:adder|addcore:adder0|result_node2
- 54 D DFFE t 1 0 0 1 5 1 4 |LAT_RECEIVE:46|count3 (|LAT_RECEIVE:46|:12)
- 60 D DFFE t 0 0 0 1 4 1 5 |LAT_RECEIVE:46|count2 (|LAT_RECEIVE:46|:13)
(41) 64 D DFFE t 0 0 0 1 4 1 3 |LAT_RECEIVE:46|count1 (|LAT_RECEIVE:46|:14)
- 63 D DFFE t 0 0 0 1 4 1 4 |LAT_RECEIVE:46|count0 (|LAT_RECEIVE:46|:15)
(40) 62 D DFFE t 0 0 0 1 1 1 0 |LAT_RECEIVE:46|t0_in_lat (|LAT_RECEIVE:46|:17)
- 55 D DFFE t 0 0 0 1 1 1 0 |LAT_RECEIVE:46|t1_in_lat (|LAT_RECEIVE:46|:18)
- 2 A TFFE t 0 0 0 0 1 0 1 |LDD_SEND:45|rclk2 (|LDD_SEND:45|:6)
(24) 33 C TFFE t 0 0 0 0 1 0 1 |LDD_SEND:45|rclk3 (|LDD_SEND:45|:7)
- 34 C TFFE t 0 0 0 0 1 1 0 |LDD_SEND:45|rclk4 (|LDD_SEND:45|:8)
- 61 D DFFE t 0 0 0 1 1 1 0 |SINGLE_RECEIVE:55|t0_in_r (|SINGLE_RECEIVE:55|:7)
- 59 D DFFE t 0 0 0 1 1 1 0 |SINGLE_RECEIVE:55|t1_in_r (|SINGLE_RECEIVE:55|:8)
- 58 D DFFE t 0 0 0 1 1 1 0 |SINGLE_RECEIVE:56|t0_in_r (|SINGLE_RECEIVE:56|:7)
(38) 56 D DFFE t 0 0 0 1 1 1 0 |SINGLE_RECEIVE:56|t1_in_r (|SINGLE_RECEIVE:56|:8)
(32) 48 C DFFE t 0 0 0 1 1 1 0 |SINGLE_RECEIVE:57|t0_in_r (|SINGLE_RECEIVE:57|:7)
- 44 C DFFE t 0 0 0 1 1 1 0 |SINGLE_RECEIVE:57|t1_in_r (|SINGLE_RECEIVE:57|:8)
- 42 C DFFE t 0 0 0 1 1 1 0 |SINGLE_RECEIVE:58|t0_in_r (|SINGLE_RECEIVE:58|:7)
(26) 36 C DFFE t 0 0 0 1 1 1 0 |SINGLE_RECEIVE:58|t1_in_r (|SINGLE_RECEIVE:58|:8)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\ljc\cpld(huaqi)\decode.rpt
decode
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+----- LC14 clk_ldd
| +--- LC2 |LDD_SEND:45|rclk2
| | +- LC11 out_ldd
| | |
| | | Other LABs fed by signals
| | | that feed LAB 'A'
LC | | | | A B C D | Logic cells that feed LAB 'A':
LC14 -> * * * | * - - - | <-- clk_ldd
Pin
43 -> * - - | * - - - | <-- clk50M
4 -> - - * | * - - - | <-- ldd_data
LC34 -> - - * | * - - - | <-- |LDD_SEND:45|rclk4
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\ljc\cpld(huaqi)\decode.rpt
decode
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+--------------- LC33 |LDD_SEND:45|rclk3
| +------------- LC34 |LDD_SEND:45|rclk4
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