📄 lat_receive.rpt
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** BURIED LOGIC **
Shareable
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Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(32) 25 B SOFT t 0 0 0 0 2 0 1 |LPM_ADD_SUB:488|addcore:adder|addcore:adder0|result_node1
(33) 24 B SOFT t 0 0 0 0 3 0 1 |LPM_ADD_SUB:488|addcore:adder|addcore:adder0|result_node2
(31) 26 B DFFE + t 1 0 0 0 5 1 4 count3 (:12)
(39) 19 B DFFE + t 0 0 0 0 4 1 5 count2 (:13)
(38) 20 B DFFE + t 0 0 0 0 4 1 3 count1 (:14)
(37) 21 B DFFE + t 0 0 0 0 4 1 4 count0 (:15)
- 22 B DFFE t 0 0 0 1 1 1 0 t0_in_lat (:17)
(34) 23 B DFFE t 0 0 0 1 1 1 0 t1_in_lat (:18)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\ljc\cpld(huaqi)\lat_receive.rpt
lat_receive
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------- LC25 |LPM_ADD_SUB:488|addcore:adder|addcore:adder0|result_node1
| +----------------- LC24 |LPM_ADD_SUB:488|addcore:adder|addcore:adder0|result_node2
| | +--------------- LC18 out_lat
| | | +------------- LC17 out_rclk
| | | | +----------- LC26 count3
| | | | | +--------- LC19 count2
| | | | | | +------- LC20 count1
| | | | | | | +----- LC21 count0
| | | | | | | | +--- LC22 t0_in_lat
| | | | | | | | | +- LC23 t1_in_lat
| | | | | | | | | |
| | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC25 -> - - - - - - * - - - | - * | <-- |LPM_ADD_SUB:488|addcore:adder|addcore:adder0|result_node1
LC24 -> - - - - - * - - - - | - * | <-- |LPM_ADD_SUB:488|addcore:adder|addcore:adder0|result_node2
LC18 -> - - * - * * * * - - | - * | <-- out_lat
LC17 -> - - * * - - - - * * | - * | <-- out_rclk
LC26 -> - - - * * * * * - - | - * | <-- count3
LC19 -> - * - * * * * * - - | - * | <-- count2
LC20 -> * * - * * - - - - - | - * | <-- count1
LC21 -> * * - * * - - * - - | - * | <-- count0
LC22 -> - - * - - - - - - - | - * | <-- t0_in_lat
LC23 -> - - * - - - - - - - | - * | <-- t1_in_lat
Pin
4 -> - - - - - - - - * * | - * | <-- in_lat
43 -> - - - - - - - - - - | - - | <-- in_rclk
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\ljc\cpld(huaqi)\lat_receive.rpt
lat_receive
** EQUATIONS **
in_lat : INPUT;
in_rclk : INPUT;
-- Node name is ':15' = 'count0'
-- Equation name is 'count0', location is LC021, type is buried.
count0 = DFFE( _EQ001 $ GND, GLOBAL( in_rclk), out_lat, VCC, VCC);
_EQ001 = !count0 & !count2 & count3
# !count0 & !count3;
-- Node name is ':14' = 'count1'
-- Equation name is 'count1', location is LC020, type is buried.
count1 = DFFE( _EQ002 $ GND, GLOBAL( in_rclk), out_lat, VCC, VCC);
_EQ002 = !count2 & count3 & _LC025
# !count3 & _LC025;
-- Node name is ':13' = 'count2'
-- Equation name is 'count2', location is LC019, type is buried.
count2 = DFFE( _EQ003 $ GND, GLOBAL( in_rclk), out_lat, VCC, VCC);
_EQ003 = !count2 & count3 & _LC024
# !count3 & _LC024;
-- Node name is ':12' = 'count3'
-- Equation name is 'count3', location is LC026, type is buried.
count3 = DFFE( _EQ004 $ GND, GLOBAL( in_rclk), out_lat, VCC, VCC);
_EQ004 = count0 & count1 & count2 & !count3
# !count2 & count3 & _X001;
_X001 = EXP( count0 & count1 & count2);
-- Node name is 'out_lat' = 'lat_temp'
-- Equation name is 'out_lat', location is LC018, type is output.
out_lat = DFFE( _EQ005 $ t0_in_lat, !out_rclk, VCC, VCC, VCC);
_EQ005 = !out_lat & t0_in_lat & t1_in_lat
# out_lat & !t0_in_lat & !t1_in_lat;
-- Node name is 'out_rclk' = 'rclk'
-- Equation name is 'out_rclk', location is LC017, type is output.
out_rclk = DFFE( _EQ006 $ _EQ007, GLOBAL(!in_rclk), VCC, VCC, VCC);
_EQ006 = count0 & count2 & count3 & !out_rclk
# count1 & count3 & !out_rclk & _X002;
_X002 = EXP(!count0 & !count2);
_EQ007 = _X003 & _X004 & _X005 & _X006;
_X003 = EXP(!count1 & !count2 & out_rclk);
_X004 = EXP(!count0 & !count2 & out_rclk);
_X005 = EXP(!count0 & !count1 & out_rclk);
_X006 = EXP(!count3 & out_rclk);
-- Node name is ':17' = 't0_in_lat'
-- Equation name is 't0_in_lat', location is LC022, type is buried.
t0_in_lat = DFFE( in_lat $ GND, out_rclk, VCC, VCC, VCC);
-- Node name is ':18' = 't1_in_lat'
-- Equation name is 't1_in_lat', location is LC023, type is buried.
t1_in_lat = DFFE( in_lat $ GND, !out_rclk, VCC, VCC, VCC);
-- Node name is '|LPM_ADD_SUB:488|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC025', type is buried
_LC025 = LCELL( count1 $ count0);
-- Node name is '|LPM_ADD_SUB:488|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC024', type is buried
_LC024 = LCELL( count2 $ _EQ008);
_EQ008 = count0 & count1;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\ljc\cpld(huaqi)\lat_receive.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX3000A' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,597K
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