mydcm.vhi

来自「it describe how to develop the field pro」· VHI 代码 · 共 26 行

-- VHDL Instantiation Created from source file MyDCM.vhd -- 11:22:44 07/11/2002
--
-- Notes: 
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit

	COMPONENT MyDCM
	PORT(
		clkin_in : IN std_logic;          
		locked_out : OUT std_logic;
		clk2x_out : OUT std_logic;
		clk0_out : OUT std_logic
		);
	END COMPONENT;

	Inst_MyDCM: MyDCM PORT MAP(
		clkin_in => ,
		locked_out => ,
		clk2x_out => ,
		clk0_out => 
	);