📄 ch_fifo.twr
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Release 5.1i - Trace F.22
Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.
Y:/XILI/QualityPartnerBuild3/bin/nt/trce.exe -quiet -e 3 -l 3 -xml ch_fifo
ch_fifo.ncd -o ch_fifo.twr ch_fifo.pcf
Design file: ch_fifo.ncd
Physical constraint file: ch_fifo.pcf
Device,speed: xc2v40,-4 (ADVANCED 1.108 2002-06-12, STEPPING level 1)
Report level: error report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
WARNING:Timing:2721 - The clock inst_mydcm_clkin_ibufg is the input to DCM
inst_mydcm_dcm_inst. inst_mydcm_clkin_ibufg has a low pulse width of 12500
ps and a high pulse width of 12500 ps. This violates the pulse width of
inst_mydcm_dcm_inst which has a maximum low pulse width of 1050 ps and a
maximum high pulse width of 1050 ps.
WARNING:Timing:2721 - The clock inst_mydcm_clkin_ibufg is the input to DCM
inst_mydcm_dcm_inst. inst_mydcm_clkin_ibufg has a low pulse width of 12500
ps and a high pulse width of 12500 ps. This violates the pulse width of
inst_mydcm_dcm_inst which has a maximum low pulse width of 1050 ps and a
maximum high pulse width of 1050 ps.
================================================================================
Timing constraint: TS_wr_clk_in = PERIOD TIMEGRP "wr_clk_in" 25 nS HIGH 50.000000 % ;
0 items analyzed, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_inst_mydcm_clk0_buf = PERIOD TIMEGRP "inst_mydcm_clk0_buf" TS_wr_clk_in *
1.000000 HIGH 50.000 % ;
441941 items analyzed, 0 timing errors detected.
Minimum period is 24.440ns.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_inst_mydcm_clk2x_buf = PERIOD TIMEGRP "inst_mydcm_clk2x_buf" TS_wr_clk_in /
2.000000 HIGH 50.000 % ;
381 items analyzed, 0 timing errors detected.
Minimum period is 5.887ns.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: OFFSET = IN 4.500 nS BEFORE COMP "wr_clk_in" ;
15 items analyzed, 0 timing errors detected.
Minimum allowable offset is 4.190ns.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: OFFSET = OUT 9 nS AFTER COMP "wr_clk_in" ;
13 items analyzed, 8 timing errors detected.
Minimum allowable offset is 9.431ns.
--------------------------------------------------------------------------------
Slack: -0.431ns (requirement - (clock arrival + clock path + data path))
Source: wr_clk_in (PAD)
Destination: rd_data<0> (PAD)
Source Clock: rd_clk rising at 0.000ns
Requirement: 9.000ns
Data Path Delay: 10.079ns (Levels of Logic = 1)
Clock Path Delay: -0.648ns (Levels of Logic = 3)
Clock Path: wr_clk_in to fifo_2048x8_inst_fifo_bram.B
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
A8.I Tiopi 0.825 wr_clk_in
wr_clk_in
inst_mydcm_clkin_ibufg_inst
DCM_X1Y1.CLKIN net (fanout=1) 0.798 inst_mydcm_clkin_ibufg
DCM_X1Y1.CLK2X Tdcmino -4.186 inst_mydcm_dcm_inst
inst_mydcm_dcm_inst
BUFGMUX7P.I0 net (fanout=1) 0.852 inst_mydcm_clk2x_buf
BUFGMUX7P.O Tgi0o 0.589 inst_mydcm_clk2x_bufg_inst
inst_mydcm_clk2x_bufg_inst.GCLKMUX
inst_mydcm_clk2x_bufg_inst
RAMB16_X1Y1.CLKB net (fanout=27) 0.474 rd_clk
------------------------------------------------- ---------------------------
Total -0.648ns (-2.772ns logic, 2.124ns route)
Data Path: fifo_2048x8_inst_fifo_bram.B to rd_data<0>
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
RAMB16_X1Y1.DOB0 Tbcko 2.647 fifo_2048x8_inst_fifo_bram
fifo_2048x8_inst_fifo_bram.B
C16.O1 net (fanout=1) 1.325 rd_data_0_obuf
C16.PAD Tioop 6.107 rd_data<0>
rd_data_0_obuf
rd_data<0>
------------------------------------------------- ---------------------------
Total 10.079ns (8.754ns logic, 1.325ns route)
(86.9% logic, 13.1% route)
--------------------------------------------------------------------------------
Slack: -0.379ns (requirement - (clock arrival + clock path + data path))
Source: wr_clk_in (PAD)
Destination: rd_data<2> (PAD)
Source Clock: rd_clk rising at 0.000ns
Requirement: 9.000ns
Data Path Delay: 10.027ns (Levels of Logic = 1)
Clock Path Delay: -0.648ns (Levels of Logic = 3)
Clock Path: wr_clk_in to fifo_2048x8_inst_fifo_bram.B
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
A8.I Tiopi 0.825 wr_clk_in
wr_clk_in
inst_mydcm_clkin_ibufg_inst
DCM_X1Y1.CLKIN net (fanout=1) 0.798 inst_mydcm_clkin_ibufg
DCM_X1Y1.CLK2X Tdcmino -4.186 inst_mydcm_dcm_inst
inst_mydcm_dcm_inst
BUFGMUX7P.I0 net (fanout=1) 0.852 inst_mydcm_clk2x_buf
BUFGMUX7P.O Tgi0o 0.589 inst_mydcm_clk2x_bufg_inst
inst_mydcm_clk2x_bufg_inst.GCLKMUX
inst_mydcm_clk2x_bufg_inst
RAMB16_X1Y1.CLKB net (fanout=27) 0.474 rd_clk
------------------------------------------------- ---------------------------
Total -0.648ns (-2.772ns logic, 2.124ns route)
Data Path: fifo_2048x8_inst_fifo_bram.B to rd_data<2>
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
RAMB16_X1Y1.DOB2 Tbcko 2.647 fifo_2048x8_inst_fifo_bram
fifo_2048x8_inst_fifo_bram.B
D15.O1 net (fanout=1) 1.273 rd_data_2_obuf
D15.PAD Tioop 6.107 rd_data<2>
rd_data_2_obuf
rd_data<2>
------------------------------------------------- ---------------------------
Total 10.027ns (8.754ns logic, 1.273ns route)
(87.3% logic, 12.7% route)
--------------------------------------------------------------------------------
Slack: -0.379ns (requirement - (clock arrival + clock path + data path))
Source: wr_clk_in (PAD)
Destination: rd_data<1> (PAD)
Source Clock: rd_clk rising at 0.000ns
Requirement: 9.000ns
Data Path Delay: 10.027ns (Levels of Logic = 1)
Clock Path Delay: -0.648ns (Levels of Logic = 3)
Clock Path: wr_clk_in to fifo_2048x8_inst_fifo_bram.B
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
A8.I Tiopi 0.825 wr_clk_in
wr_clk_in
inst_mydcm_clkin_ibufg_inst
DCM_X1Y1.CLKIN net (fanout=1) 0.798 inst_mydcm_clkin_ibufg
DCM_X1Y1.CLK2X Tdcmino -4.186 inst_mydcm_dcm_inst
inst_mydcm_dcm_inst
BUFGMUX7P.I0 net (fanout=1) 0.852 inst_mydcm_clk2x_buf
BUFGMUX7P.O Tgi0o 0.589 inst_mydcm_clk2x_bufg_inst
inst_mydcm_clk2x_bufg_inst.GCLKMUX
inst_mydcm_clk2x_bufg_inst
RAMB16_X1Y1.CLKB net (fanout=27) 0.474 rd_clk
------------------------------------------------- ---------------------------
Total -0.648ns (-2.772ns logic, 2.124ns route)
Data Path: fifo_2048x8_inst_fifo_bram.B to rd_data<1>
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
RAMB16_X1Y1.DOB1 Tbcko 2.647 fifo_2048x8_inst_fifo_bram
fifo_2048x8_inst_fifo_bram.B
D16.O1 net (fanout=1) 1.273 rd_data_1_obuf
D16.PAD Tioop 6.107 rd_data<1>
rd_data_1_obuf
rd_data<1>
------------------------------------------------- ---------------------------
Total 10.027ns (8.754ns logic, 1.273ns route)
(87.3% logic, 12.7% route)
--------------------------------------------------------------------------------
1 constraint not met.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Setup/Hold to clock wr_clk_in
---------------+------------+------------+
| Setup to | Hold to |
Source Pad | clk (edge) | clk (edge) |
---------------+------------+------------+
data_ch | 1.840(R)| -0.765(R)|
rd | 3.939(R)| -3.115(R)|
reset | 4.190(R)| -3.421(R)|
---------------+------------+------------+
Clock wr_clk_in to Pad
---------------+------------+
| clk (edge) |
Destination Pad| to PAD |
---------------+------------+
almost_empty | 5.882(R)|
almost_full | 5.883(R)|
empty | 5.883(R)|
full | 5.883(R)|
pn_lock_rd_clk | 6.992(R)|
rd_data<0> | 9.431(R)|
rd_data<1> | 9.379(R)|
rd_data<2> | 9.379(R)|
rd_data<3> | 9.163(R)|
rd_data<4> | 9.083(R)|
rd_data<5> | 9.163(R)|
rd_data<6> | 9.345(R)|
rd_data<7> | 9.378(R)|
---------------+------------+
Clock to Setup on destination clock wr_clk_in
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
wr_clk_in | 24.440| | | |
---------------+---------+---------+---------+---------+
Timing summary:
---------------
Timing errors: 8 Score: 2321
Constraints cover 442350 paths, 0 nets, and 990 connections (95.0% coverage)
Design statistics:
Minimum period: 24.440ns (Maximum frequency: 40.917MHz)
Minimum input arrival time before clock: 4.190ns
Minimum output required time after clock: 9.431ns
Analysis completed Thu Jul 18 14:52:01 2002
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