📄 ch_fifo.par
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Release 5.1i - Par F.22Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.SJC-XILIADM2:: Thu Jul 18 14:51:29 2002Y:/XILI/QualityPartnerBuild3/bin/nt/par.exe -w -ol 2 -t 1 ch_fifo_map.ncd
ch_fifo.ncd ch_fifo.pcf Constraints file: ch_fifo.pcfLoading device database for application par from file "ch_fifo_map.ncd". "ch_fifo" is an NCD, version 2.37, device xc2v40, package fg256, speed -4Loading device for application par from file '2v40.nph' in environment
Y:/XILI/QualityPartnerBuild3.The STEPPING level for this design is 1.Device speed data version: ADVANCED 1.108 2002-06-12.Resolved that DCM <inst_mydcm_dcm_inst> must be placed at site DCM_X1Y1.Resolved that RAMB16 <fifo_2048x8_inst_fifo_bram> must be placed at site
RAMB16_X1Y1.Device utilization summary: Number of External IOBs 17 out of 88 19% Number of LOCed External IOBs 0 out of 17 0% Number of RAMB16s 1 out of 4 25% Number of SLICEs 174 out of 256 67% Number of BUFGMUXs 2 out of 16 12% Number of DCMs 1 out of 4 25%Overall effort level (-ol): 2 (set by user)Placer effort level (-pl): 2 (set by user)Placer cost table entry (-t): 1Router effort level (-rl): 2 (set by user)Starting initial Timing Analysis. REAL time: 3 secs WARNING:Timing:2721 - The clock inst_mydcm_clkin_ibufg is the input to DCM
inst_mydcm_dcm_inst. inst_mydcm_clkin_ibufg has a low pulse width of 12500
ps and a high pulse width of 12500 ps. This violates the pulse width of
inst_mydcm_dcm_inst which has a maximum low pulse width of 1050 ps and a
maximum high pulse width of 1050 ps.WARNING:Timing:2721 - The clock inst_mydcm_clkin_ibufg is the input to DCM
inst_mydcm_dcm_inst. inst_mydcm_clkin_ibufg has a low pulse width of 12500
ps and a high pulse width of 12500 ps. This violates the pulse width of
inst_mydcm_dcm_inst which has a maximum low pulse width of 1050 ps and a
maximum high pulse width of 1050 ps.Finished initial Timing Analysis. REAL time: 4 secs Phase 1.1Phase 1.1 (Checksum:989c16) REAL time: 4 secs Phase 3.23......Phase 3.23 (Checksum:989682) REAL time: 8 secs Phase 4.3Phase 4.3 (Checksum:26259fc) REAL time: 8 secs Phase 5.5Phase 5.5 (Checksum:2faf07b) REAL time: 8 secs Phase 6.8..........................................................................................................................................Phase 6.8 (Checksum:9c6633) REAL time: 9 secs Phase 7.5Phase 7.5 (Checksum:42c1d79) REAL time: 9 secs Phase 8.18Phase 8.18 (Checksum:4c4b3f8) REAL time: 9 secs Phase 9.24Phase 9.24 (Checksum:55d4a77) REAL time: 9 secs Writing design to file ch_fifo.ncd.Total REAL time to Placer completion: 10 secs Total CPU time to Placer completion: 8 secs Starting Router REAL time: 10 secs Phase 1: 1080 unrouted; REAL time: 10 secs Phase 2: 984 unrouted; REAL time: 10 secs Phase 3: 233 unrouted; (~5162) REAL time: 10 secs Phase 4: 235 unrouted; (~2321) REAL time: 11 secs Phase 5: 238 unrouted; (~2321) REAL time: 11 secs Writing design to file ch_fifo.ncd.Phase 6: 0 unrouted; (~2321) REAL time: 12 secs Phase 7: 0 unrouted; (~2321) REAL time: 14 secs Phase 8: 0 unrouted; (~2321) REAL time: 16 secs Finished Router REAL time: 16 secs Total REAL time to Router completion: 16 secs Total CPU time to Router completion: 15 secs Generating "par" statistics.**************************Generating Clock Report**************************+----------------------------+----------+--------+------------+-------------+| Clock Net | Resource | Fanout |Max Skew(ns)|Max Delay(ns)|+----------------------------+----------+--------+------------+-------------+| wr_clk | Global | 28 | 0.206 | 0.656 |+----------------------------+----------+--------+------------+-------------+| rd_clk | Global | 27 | 0.203 | 0.653 |+----------------------------+----------+--------+------------+-------------+ The Delay Summary Report The Score for this design is: 8164The Number of signals not completely routed for this design is: 0 The Average Connection Delay for this design is: 0.736 ns The Maximum Pin Delay is: 3.069 ns The Average Connection Delay on the 10 Worst Nets is: 2.216 ns Listing Pin Delays by value: (ns) d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 5.00 d >= 5.00 --------- --------- --------- --------- --------- --------- 821 229 29 1 0 0Timing Score: 2321WARNING:Par:62 - Timing constraints have not been met.Asterisk (*) preceding a constraint indicates it was not met.-------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels-------------------------------------------------------------------------------- TS_wr_clk_in = PERIOD TIMEGRP "wr_clk_in" | | | 25 nS HIGH 50.000000 % | | | -------------------------------------------------------------------------------- TS_inst_mydcm_clk0_buf = PERIOD TIMEGRP " | 25.000ns | 24.440ns | 20 inst_mydcm_clk0_buf" TS_wr_clk_in * 1.00 | | | 0000 HIGH 50.000 % | | | -------------------------------------------------------------------------------- TS_inst_mydcm_clk2x_buf = PERIOD TIMEGRP | 12.500ns | 5.887ns | 3 "inst_mydcm_clk2x_buf" TS_wr_clk_in / 2. | | | 000000 HIGH 50.000 % | | | -------------------------------------------------------------------------------- OFFSET = IN 4.500 nS BEFORE COMP "wr_clk | 4.500ns | 4.190ns | 1 _in" | | | --------------------------------------------------------------------------------* OFFSET = OUT 9 nS AFTER COMP "wr_clk_in" | 9.000ns | 9.431ns | 1 --------------------------------------------------------------------------------1 constraint not met.All signals are completely routed.Total REAL time to PAR completion: 19 secs Total CPU time to PAR completion: 16 secs Placement: Completed - No errors found.Routing: Completed - No errors found.Timing: Completed - 8 errors found.Writing design to file ch_fifo.ncd.PAR done.⌨️ 快捷键说明
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