mydcm.v

it describe how to develop the field programmable gate array

// Module MyDCM
// Generated by Xilinx Architecture Wizard
// Verilog
// Written for synthesis tool: XST
// Xilinx device: xc2v40-4fg256

module MyDCM(LOCKED_OUT, CLKIN_IN, CLK2X_OUT, CLK0_OUT);

input CLKIN_IN;

output LOCKED_OUT;
output CLK2X_OUT;
output CLK0_OUT;

wire CLKIN_IBUFG;
wire CLKFB_IN;
wire CLK0_BUF;
wire CLK2X_BUF;

assign CLK0_OUT = CLKFB_IN;

DCM MyDCM_inst(
    .CLKIN (CLKIN_IBUFG),
    .CLKFB (CLKFB_IN),
    .RST (1'b0),
    .PSEN (1'b0),
    .PSINCDEC (1'b0),
    .PSCLK (1'b0),
    .DSSEN (1'b0),
    .CLK0 (CLK0_BUF),
    .CLK90 (),
    .CLK180 (),
    .CLK270 (),
    .CLKDV (),
    .CLK2X (CLK2X_BUF),
    .CLK2X180 (),
    .CLKFX (),
    .CLKFX180 (),
    .STATUS (),
    .LOCKED (LOCKED_OUT),
    .PSDONE ());
// synthesis attribute CLK_FEEDBACK of MyDCM_inst is "1X"
// synthesis attribute CLKDV_DIVIDE of MyDCM_inst is 2
// synthesis attribute CLKFX_DIVIDE of MyDCM_inst is 1
// synthesis attribute CLKFX_MULTIPLY of MyDCM_inst is 4
// synthesis attribute CLKIN_DIVIDE_BY_2 of MyDCM_inst is "FALSE"
// synthesis attribute CLKIN_PERIOD of MyDCM_inst is 10
// synthesis attribute CLKOUT_PHASE_SHIFT of MyDCM_inst is "NONE"
// synthesis attribute DESKEW_ADJUST of MyDCM_inst is "SYSTEM_SYNCHRONOUS"
// synthesis attribute DFS_FREQUENCY_MODE of MyDCM_inst is "LOW"
// synthesis attribute DLL_FREQUENCY_MODE of MyDCM_inst is "LOW"
// synthesis attribute DUTY_CYCLE_CORRECTION of MyDCM_inst is "TRUE"
// synthesis attribute PHASE_SHIFT of MyDCM_inst is 0
// synthesis attribute STARTUP_WAIT of MyDCM_inst is "FALSE"
// synthesis translate_off
 defparam MyDCM_inst.CLK_FEEDBACK="1X";
 defparam MyDCM_inst.CLKDV_DIVIDE=2;
 defparam MyDCM_inst.CLKFX_DIVIDE=1;
 defparam MyDCM_inst.CLKFX_MULTIPLY=4;
 defparam MyDCM_inst.CLKIN_DIVIDE_BY_2="FALSE";
 defparam MyDCM_inst.CLKIN_PERIOD=10;
 defparam MyDCM_inst.CLKOUT_PHASE_SHIFT="NONE";
 defparam MyDCM_inst.DESKEW_ADJUST="SYSTEM_SYNCHRONOUS";
 defparam MyDCM_inst.DFS_FREQUENCY_MODE="LOW";
 defparam MyDCM_inst.DLL_FREQUENCY_MODE="LOW";
 defparam MyDCM_inst.DUTY_CYCLE_CORRECTION="TRUE";
 defparam MyDCM_inst.PHASE_SHIFT=0;
 defparam MyDCM_inst.STARTUP_WAIT="FALSE";
// synthesis translate_on

IBUFG CLKIN_IBUFG_INST(
    .I (CLKIN_IN),
    .O (CLKIN_IBUFG));

BUFG CLK0_BUFG_INST(
    .I (CLK0_BUF),
    .O (CLKFB_IN));

BUFG CLK2X_BUFG_INST(
    .I (CLK2X_BUF),
    .O (CLK2X_OUT));

endmodule