ch_fifo.bld

it describe how to develop the field programmable gate array

Release 5.1i - ngdbuild F.22
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild -quiet -dd u:\v5\labs\timing_const\verilog/_ngo -uc
myucf.ucf -insert_keep_hierarchy -p xc2v40-fg256-4 ch_fifo.ngc ch_fifo.ngd 

Reading NGO file "U:/v5/labs/timing_const/verilog/ch_fifo.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "myucf.ucf" ...

Checking timing specifications ...
INFO:XdmHelpers:851 - TNM "wr_clk_in", used in period specification
   "TS_wr_clk_in", was traced into DCM instance "MyDCM_inst_MyDCM_inst". The
   following new TNM groups and period specifications were generated at the DCM
   output(s):
   CLK0: TS_MyDCM_inst_CLK0_BUF=PERIOD MyDCM_inst_CLK0_BUF TS_wr_clk_in*1.000000
HIGH 50.000000%
   CLK2X: TS_MyDCM_inst_CLK2X_BUF=PERIOD MyDCM_inst_CLK2X_BUF
TS_wr_clk_in/2.000000 HIGH 50.000000%
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "ch_fifo.ngd" ...

Writing NGDBUILD log file "ch_fifo.bld"...