ch_fifo.syr

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  11-bit register                  : 3
# Counters                         : 2
  11-bit up counter                : 2
# Multiplexers                     : 14
  2-to-1 multiplexer               : 14
# Adders/Subtractors               : 18
  4-bit subtractor                 : 1
  1-bit adder carry out            : 2
  2-bit adder                      : 2
  2-bit adder carry out            : 2
  3-bit adder                      : 7
  3-bit adder carry out            : 2
  11-bit adder                     : 1
  11-bit subtractor                : 1
# Comparators                      : 3
  11-bit comparator greatequal     : 2
  11-bit comparator lessequal      : 1

=========================================================================

WARNING:Xst:524 - All outputs of the instance <Madd__n0043> of the block <LPM_ADD_SUB_6> are unconnected in block <pn_correlation>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <Madd__n0024> of the block <LPM_ADD_SUB_5> are unconnected in block <pn_correlation>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <Madd__n0023> of the block <LPM_ADD_SUB_5> are unconnected in block <pn_correlation>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <Madd__n0021> of the block <LPM_ADD_SUB_5> are unconnected in block <pn_correlation>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <Madd__n0020> of the block <LPM_ADD_SUB_5> are unconnected in block <pn_correlation>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <Madd__n0041> of the block <LPM_ADD_SUB_4> are unconnected in block <pn_correlation>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <Madd__n0040> of the block <LPM_ADD_SUB_4> are unconnected in block <pn_correlation>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <Madd__n0013> of the block <LPM_ADD_SUB_3> are unconnected in block <pn_correlation>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <Madd__n0012> of the block <LPM_ADD_SUB_3> are unconnected in block <pn_correlation>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <Madd__n0039> of the block <LPM_ADD_SUB_2> are unconnected in block <pn_correlation>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <Madd__n0038> of the block <LPM_ADD_SUB_2> are unconnected in block <pn_correlation>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <Mmux__old_disagree_16> of the block <LPM_MUX2_4> are unconnected in block <pn_correlation>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <Mmux__old_agree_15> of the block <LPM_MUX2_4> are unconnected in block <pn_correlation>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <Mmux__old_agree_14> of the block <LPM_MUX2_3> are unconnected in block <pn_correlation>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <Mmux__old_disagree_13> of the block <LPM_MUX2_3> are unconnected in block <pn_correlation>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <Mmux__old_agree_12> of the block <LPM_MUX2_3> are unconnected in block <pn_correlation>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <Mmux__old_disagree_11> of the block <LPM_MUX2_3> are unconnected in block <pn_correlation>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <Mmux__old_agree_10> of the block <LPM_MUX2_3> are unconnected in block <pn_correlation>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <Mmux__old_disagree_9> of the block <LPM_MUX2_3> are unconnected in block <pn_correlation>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <Mmux__old_agree_8> of the block <LPM_MUX2_3> are unconnected in block <pn_correlation>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <Mmux__old_disagree_7> of the block <LPM_MUX2_3> are unconnected in block <pn_correlation>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <Mmux__old_agree_6> of the block <LPM_MUX2_2> are unconnected in block <pn_correlation>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <Mmux__old_disagree_5> of the block <LPM_MUX2_2> are unconnected in block <pn_correlation>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <Mmux__old_agree_4> of the block <LPM_MUX2_2> are unconnected in block <pn_correlation>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <Mmux__old_disagree_3> of the block <LPM_MUX2_2> are unconnected in block <pn_correlation>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <Madd__n0042> of the block <LPM_ADD_SUB_6> are unconnected in block <pn_correlation>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <Madd__n0026> of the block <LPM_ADD_SUB_5> are unconnected in block <pn_correlation>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <Madd__n0027> of the block <LPM_ADD_SUB_5> are unconnected in block <pn_correlation>.
   This instance will be removed from the design along with all underlying logic
=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1293 - FF/Latch  <pn_fnd> is constant in block <pn_correlation>.
Library "Y:/XILI/QualityPartnerBuild3/data/librtl.xst" Consulted
WARNING:Xst:1291 - FF/Latch <half_full> is unconnected in block <fifo_status_inst>.

Optimizing unit <ch_fifo> ...

Optimizing unit <fifo_status> ...

Optimizing unit <pn_correlation_fsm> ...

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <fifo_status_inst_half_full> is unconnected in block <ch_fifo>.
Loading device for application Xst from file '2v40.nph' in environment Y:/XILI/QualityPartnerBuild3.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block ch_fifo, actual ratio is 25.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Output File Name               : ch_fifo.ngr
Top Level Output File Name         : ch_fifo
Output Format                      : NGC
Optimization Criterion             : Speed
Keep Hierarchy                     : NO
Macro Generator                    : macro+

Design Statistics
# IOs                              : 17

Macro Statistics :
# Registers                        : 28
#      1-bit register              : 23
#      11-bit register             : 3
#      3-bit register              : 1
#      4-bit register              : 1
# Counters                         : 2
#      11-bit up counter           : 2
# Adders/Subtractors               : 2
#      11-bit adder                : 1
#      11-bit subtractor           : 1
# Comparators                      : 3
#      11-bit comparator greatequal: 2
#      11-bit comparator lessequal : 1

Cell Usage :
# BELS                             : 192
#      GND                         : 1
#      LUT1                        : 12
#      LUT2                        : 13
#      LUT2_D                      : 2
#      LUT2_L                      : 20
#      LUT3                        : 18
#      LUT3_D                      : 2
#      LUT3_L                      : 11
#      LUT4                        : 14
#      LUT4_L                      : 13
#      MUXCY                       : 41
#      MUXF5                       : 1
#      VCC                         : 1
#      XORCY                       : 43
# FlipFlops/Latches                : 83
#      FDC                         : 49
#      FDCE                        : 11
#      FDCPE                       : 22
#      FDP                         : 1
# RAMS                             : 1
#      RAMB16_S9_S9                : 1
# Clock Buffers                    : 2
#      BUFG                        : 2
# IO Buffers                       : 17
#      IBUF                        : 3
#      IBUFG                       : 1
#      OBUF                        : 13
# DCMs                             : 1
#      DCM                         : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2v40fg256-4 

 Number of Slices:                      66  out of    256    25%  
 Number of Slice Flip Flops:            83  out of    512    16%  
 Number of 4 input LUTs:               105  out of    512    20%  
 Number of bonded IOBs:                 17  out of     88    19%  
 Number of BRAMs:                        1  out of      4    25%  
 Number of GCLKs:                        2  out of     16    12%  
 Number of DCMs:                         1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
wr_clk_in                          | MyDCM_inst_MyDCM_inst:CLK0| 40    |
wr_clk_in                          | MyDCM_inst_MyDCM_inst:CLK2X| 44    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 11.320ns (Maximum Frequency: 88.339MHz)
   Minimum input arrival time before clock: 4.769ns
   Maximum output required time after clock: 9.114ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'wr_clk_in'
Delay:               5.660ns (Levels of Logic = 12)
  Source:            fifo_status_inst_pn_lock_rd_clk
  Destination:       fifo_status_inst_rd_addr_10
  Source Clock:      wr_clk_in rising 2.0X
  Destination Clock: wr_clk_in rising 2.0X

  Data Path: fifo_status_inst_pn_lock_rd_clk to fifo_status_inst_rd_addr_10
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             25   0.568   2.234  fifo_status_inst_pn_lock_rd_clk (fifo_status_inst_pn_lock_rd_clk)
     LUT3_L:I0->LO         1   0.439   0.000  fifo_status_inst_rd_addr_inst_lut3_01 (fifo_status_inst_rd_addr_inst_lut3_0)
     MUXCY:S->O            1   0.298   0.000  fifo_status_inst_rd_addr_inst_cy_1 (fifo_status_inst_rd_addr_inst_cy_1)
     MUXCY:CI->O           1   0.053   0.000  fifo_status_inst_rd_addr_inst_cy_2 (fifo_status_inst_rd_addr_inst_cy_2)
     MUXCY:CI->O           1   0.053   0.000  fifo_status_inst_rd_addr_inst_cy_3 (fifo_status_inst_rd_addr_inst_cy_3)
     MUXCY:CI->O           1   0.053   0.000  fifo_status_inst_rd_addr_inst_cy_4 (fifo_status_inst_rd_addr_inst_cy_4)
     MUXCY:CI->O           1   0.053   0.000  fifo_status_inst_rd_addr_inst_cy_5 (fifo_status_inst_rd_addr_inst_cy_5)
     MUXCY:CI->O           1   0.053   0.000  fifo_status_inst_rd_addr_inst_cy_6 (fifo_status_inst_rd_addr_inst_cy_6)
     MUXCY:CI->O           1   0.053   0.000  fifo_status_inst_rd_addr_inst_cy_7 (fifo_status_inst_rd_addr_inst_cy_7)
     MUXCY:CI->O           1   0.053   0.000  fifo_status_inst_rd_addr_inst_cy_8 (fifo_status_inst_rd_addr_inst_cy_8)
     MUXCY:CI->O           1   0.053   0.000  fifo_status_inst_rd_addr_inst_cy_9 (fifo_status_inst_rd_addr_inst_cy_9)
     MUXCY:CI->O           0   0.053   0.000  fifo_status_inst_rd_addr_inst_cy_10 (fifo_status_inst_rd_addr_inst_cy_10)
     XORCY:CI->O           1   1.274   0.000  fifo_status_inst_rd_addr_inst_sum_10 (fifo_status_inst_rd_addr_inst_sum_10)
     FDCPE:D                   0.370          fifo_status_inst_rd_addr_10
    ----------------------------------------
    Total                      5.660ns (3.426ns logic, 2.234ns route)
                                       (60.5% logic, 39.5% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'wr_clk_in'
Offset:              4.769ns (Levels of Logic = 1)
  Source:            reset
  Destination:       fifo_2048x8_inst_FIFO_BRAM
  Destination Clock: wr_clk_in rising 2.0X

  Data Path: reset to fifo_2048x8_inst_FIFO_BRAM
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            85   0.825   2.294  reset_IBUF (reset_IBUF)
     RAMB16_S9_S9:SSRA         1.650          fifo_2048x8_inst_FIFO_BRAM
    ----------------------------------------
    Total                      4.769ns (2.475ns logic, 2.294ns route)
                                       (51.9% logic, 48.1% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'wr_clk_in'
Offset:              9.114ns (Levels of Logic = 1)
  Source:            fifo_2048x8_inst_FIFO_BRAM
  Destination:       rd_data<1>
  Source Clock:      wr_clk_in rising 2.0X

  Data Path: fifo_2048x8_inst_FIFO_BRAM to rd_data<1>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     RAMB16_S9_S9:CLKB->DOB1    1   2.599   0.408  fifo_2048x8_inst_FIFO_BRAM (rd_data_1_OBUF)
     OBUF:I->O                 6.107          rd_data_1_OBUF (rd_data<1>)
    ----------------------------------------
    Total                      9.114ns (8.706ns logic, 0.408ns route)
                                       (95.5% logic, 4.5% route)

=========================================================================
CPU : 7.23 / 12.39 s | Elapsed : 7.00 / 12.00 s
 
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Total memory usage is 70332 kilobytes