ch_fifo.syr

it describe how to develop the field programmable gate array

Release 5.1i - xst F.22
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 4.20 s | Elapsed : 0.00 / 4.00 s
 
--> Reading design: ch_fifo.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Low Level Synthesis
  6) Final Report
     6.1) Device utilization summary
     6.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : ch_fifo.prj
Input Format                       : VERILOG
Ignore Synthesis Constraint File   : NO
Verilog Search Path                : 
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : ch_fifo
Output Format                      : NGC
Target Device                      : xc2v40-4fg256

---- Source Options
Top Module Name                    : ch_fifo
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Top module area constraint         : 100
Top module allowed area overflow   : 5

---- Other Options
read_cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "ch_fifo.prj"
Compiling include file "MyDCM.v"
Module <MyDCM> compiled
Compiling include file "fifo_2048x8.v"
Module <fifo_2048x8> compiled
Compiling include file "fifo_status.v"
Module <fifo_status> compiled
Compiling include file "pn_correlation.v"
Module <pn_correlation> compiled
Compiling include file "pn_correlation_fsm.v"
Module <pn_correlation_fsm> compiled
Compiling include file "pn_correlator.v"
Module <pn_correlator> compiled
Compiling include file "ch_fifo.v"
Module <ch_fifo> compiled
Compiling include file "Y:/XILI/QualityPartnerBuild3/verilog/src/iSE/unisim_comp.v"
No errors in compilation

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analysis of file <ch_fifo.prj> succeeded.
 
 
Analyzing module <DCM>.
 
Analyzing module <IBUFG>.
 
Analyzing module <BUFG>.
 
Analyzing module <MyDCM>.
Module <MyDCM> is correct for synthesis.
    Set user-defined property "CLK_FEEDBACK =  1X" for instance <MyDCM_inst> in unit <MyDCM>.
    Set user-defined property "CLKDV_DIVIDE =  2" for instance <MyDCM_inst> in unit <MyDCM>.
    Set user-defined property "CLKFX_DIVIDE =  1" for instance <MyDCM_inst> in unit <MyDCM>.
    Set user-defined property "CLKFX_MULTIPLY =  4" for instance <MyDCM_inst> in unit <MyDCM>.
    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <MyDCM_inst> in unit <MyDCM>.
    Set user-defined property "CLKIN_PERIOD =  10" for instance <MyDCM_inst> in unit <MyDCM>.
    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <MyDCM_inst> in unit <MyDCM>.
    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <MyDCM_inst> in unit <MyDCM>.
    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <MyDCM_inst> in unit <MyDCM>.
    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <MyDCM_inst> in unit <MyDCM>.
    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <MyDCM_inst> in unit <MyDCM>.
    Set user-defined property "PHASE_SHIFT =  0" for instance <MyDCM_inst> in unit <MyDCM>.
    Set user-defined property "STARTUP_WAIT =  FALSE" for instance <MyDCM_inst> in unit <MyDCM>.
 
Analyzing module <pn_correlation>.
Module <pn_correlation> is correct for synthesis.
 
Analyzing module <pn_correlation_fsm>.
Module <pn_correlation_fsm> is correct for synthesis.
 
Analyzing module <pn_correlator>.
Module <pn_correlator> is correct for synthesis.
 
Analyzing module <fifo_status>.
Module <fifo_status> is correct for synthesis.
 
Analyzing module <RAMB16_S9_S9>.
 
Analyzing module <fifo_2048x8>.
Module <fifo_2048x8> is correct for synthesis.
 
Analyzing top module <ch_fifo>.
Module <ch_fifo> is correct for synthesis.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================
INFO:Xst:1304 - Contents of register <j> in unit <pn_correlation> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <i> in unit <pn_correlation> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <j> in unit <pn_correlation_fsm> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <k> in unit <pn_correlation_fsm> never changes during circuit operation. The register is replaced by logic.

Synthesizing Unit <MyDCM>.
    Related source file is MyDCM.v.
Unit <MyDCM> synthesized.


Synthesizing Unit <pn_correlation>.
    Related source file is pn_correlation.v.
WARNING:Xst:646 - Signal <j> is assigned but never used.
WARNING:Xst:646 - Signal <result<0>> is assigned but never used.
WARNING:Xst:646 - Signal <result<1>> is assigned but never used.
WARNING:Xst:646 - Signal <result<2>> is assigned but never used.
WARNING:Xst:646 - Signal <result<3>> is assigned but never used.
WARNING:Xst:646 - Signal <result<4>> is assigned but never used.
WARNING:Xst:646 - Signal <result<5>> is assigned but never used.
WARNING:Xst:646 - Signal <result<6>> is assigned but never used.
WARNING:Xst:646 - Signal <result<7>> is assigned but never used.
WARNING:Xst:646 - Signal <agree> is assigned but never used.
WARNING:Xst:646 - Signal <disagree> is assigned but never used.
WARNING:Xst:646 - Signal <i> is assigned but never used.
WARNING:Xst:646 - Signal <correlation> is assigned but never used.
    Found 1-bit register for signal <pn_fnd>.
    Found 2-bit adder for signal <$n0012> created at line 45.
    Found 2-bit adder for signal <$n0013> created at line 46.
    Found 3-bit adder for signal <$n0020> created at line 45.
    Found 3-bit adder for signal <$n0021> created at line 46.
    Found 3-bit adder for signal <$n0023> created at line 45.
    Found 3-bit adder for signal <$n0024> created at line 46.
    Found 3-bit adder for signal <$n0026> created at line 45.
    Found 3-bit adder for signal <$n0027> created at line 46.
    Found 1-bit adder carry out for signal <$n0038> created at line 45.
    Found 1-bit adder carry out for signal <$n0039> created at line 46.
    Found 2-bit adder carry out for signal <$n0040> created at line 45.
    Found 2-bit adder carry out for signal <$n0041> created at line 46.
    Found 3-bit adder carry out for signal <$n0042> created at line 46.
    Found 3-bit adder carry out for signal <$n0043> created at line 45.
    Found 4-bit subtractor for signal <$old_correlation_17>.
    Found 8-bit register for signal <sr_data>.
    Found 40 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   9 D-type flip-flop(s).
	inferred  15 Adder/Subtracter(s).
Unit <pn_correlation> synthesized.


Synthesizing Unit <pn_correlation_fsm>.
    Related source file is pn_correlation_fsm.v.
WARNING:Xst:646 - Signal <j> is assigned but never used.
WARNING:Xst:646 - Signal <k> is assigned but never used.
    Using one-hot encoding for signal <cs>.
    Using one-hot encoding for signal <ns>.
    Found 1-bit register for signal <pn_acq>.
    Found 1-bit register for signal <wr>.
    Found 3-bit adder for signal <$n0004>.
    Found 11-bit adder for signal <$n0005>.
    Found 4-bit register for signal <cs>.
    Found 3-bit register for signal <eight_cnt>.
    Found 1-bit register for signal <pn_acq_q0>.
    Found 11-bit register for signal <pn_addr_cntr>.
    Summary:
	inferred  17 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
Unit <pn_correlation_fsm> synthesized.


Synthesizing Unit <pn_correlator>.
    Related source file is pn_correlator.v.
Unit <pn_correlator> synthesized.


Synthesizing Unit <fifo_status>.
    Related source file is fifo_status.v.
    Found 1-bit register for signal <almost_empty>.
    Found 1-bit register for signal <almost_full>.
    Found 1-bit register for signal <empty>.
    Found 1-bit register for signal <full>.
    Found 1-bit register for signal <half_full>.
    Found 1-bit register for signal <pn_lock_rd_clk>.
    Found 11-bit up counter for signal <rd_addr>.
    Found 11-bit up counter for signal <wr_addr>.
    Found 11-bit comparator greatequal for signal <$n0012> created at line 123.
    Found 11-bit comparator greatequal for signal <$n0013> created at line 121.
    Found 11-bit comparator lessequal for signal <$n0015> created at line 127.
    Found 11-bit subtractor for signal <$n0016> created at line 95.
    Found 11-bit register for signal <flag_cnt>.
    Found 11-bit register for signal <flag_wr_addr>.
    Found 1-bit register for signal <pn_lock_rd_clk_p0>.
    Found 4-bit register for signal <wr_dtct>.
    Summary:
	inferred   2 Counter(s).
	inferred  33 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred   3 Comparator(s).
Unit <fifo_status> synthesized.


Synthesizing Unit <fifo_2048x8>.
    Related source file is fifo_2048x8.v.
Unit <fifo_2048x8> synthesized.


Synthesizing Unit <ch_fifo>.
    Related source file is ch_fifo.v.
Unit <ch_fifo> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 25
  1-bit register                   : 19
  4-bit register                   : 2
  3-bit register                   : 1