ch_fifo.twr

it describe how to develop the field programmable gate array

    RAMB16_X1Y1.CLKB     net (fanout=27)       0.474   rd_clk
    -------------------------------------------------  ---------------------------
    Total                                     -0.648ns (-2.772ns logic, 2.124ns route)

  Data Path: fifo_2048x8_inst_FIFO_BRAM.B to rd_data<0>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    RAMB16_X1Y1.DOB0     Tbcko                 2.647   fifo_2048x8_inst_FIFO_BRAM
                                                       fifo_2048x8_inst_FIFO_BRAM.B
    C16.O1               net (fanout=1)        1.325   rd_data_0_OBUF
    C16.PAD              Tioop                 6.107   rd_data<0>
                                                       rd_data_0_OBUF
                                                       rd_data<0>
    -------------------------------------------------  ---------------------------
    Total                                     10.079ns (8.754ns logic, 1.325ns route)
                                                       (86.9% logic, 13.1% route)

--------------------------------------------------------------------------------
Slack:                  -0.379ns (requirement - (clock arrival + clock path + data path))
  Source:               wr_clk_in (PAD)
  Destination:          rd_data<1> (PAD)
  Source Clock:         rd_clk rising at 0.000ns
  Requirement:          9.000ns
  Data Path Delay:      10.027ns (Levels of Logic = 1)
  Clock Path Delay:     -0.648ns (Levels of Logic = 3)

  Clock Path: wr_clk_in to fifo_2048x8_inst_FIFO_BRAM.B
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    A8.I                 Tiopi                 0.825   wr_clk_in
                                                       wr_clk_in
                                                       MyDCM_inst_CLKIN_IBUFG_INST
    DCM_X1Y1.CLKIN       net (fanout=1)        0.798   MyDCM_inst_CLKIN_IBUFG
    DCM_X1Y1.CLK2X       Tdcmino              -4.186   MyDCM_inst_MyDCM_inst
                                                       MyDCM_inst_MyDCM_inst
    BUFGMUX7P.I0         net (fanout=1)        0.852   MyDCM_inst_CLK2X_BUF
    BUFGMUX7P.O          Tgi0o                 0.589   MyDCM_inst_CLK2X_BUFG_INST
                                                       MyDCM_inst_CLK2X_BUFG_INST.GCLKMUX
                                                       MyDCM_inst_CLK2X_BUFG_INST
    RAMB16_X1Y1.CLKB     net (fanout=27)       0.474   rd_clk
    -------------------------------------------------  ---------------------------
    Total                                     -0.648ns (-2.772ns logic, 2.124ns route)

  Data Path: fifo_2048x8_inst_FIFO_BRAM.B to rd_data<1>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    RAMB16_X1Y1.DOB1     Tbcko                 2.647   fifo_2048x8_inst_FIFO_BRAM
                                                       fifo_2048x8_inst_FIFO_BRAM.B
    D16.O1               net (fanout=1)        1.273   rd_data_1_OBUF
    D16.PAD              Tioop                 6.107   rd_data<1>
                                                       rd_data_1_OBUF
                                                       rd_data<1>
    -------------------------------------------------  ---------------------------
    Total                                     10.027ns (8.754ns logic, 1.273ns route)
                                                       (87.3% logic, 12.7% route)

--------------------------------------------------------------------------------
Slack:                  -0.379ns (requirement - (clock arrival + clock path + data path))
  Source:               wr_clk_in (PAD)
  Destination:          rd_data<2> (PAD)
  Source Clock:         rd_clk rising at 0.000ns
  Requirement:          9.000ns
  Data Path Delay:      10.027ns (Levels of Logic = 1)
  Clock Path Delay:     -0.648ns (Levels of Logic = 3)

  Clock Path: wr_clk_in to fifo_2048x8_inst_FIFO_BRAM.B
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    A8.I                 Tiopi                 0.825   wr_clk_in
                                                       wr_clk_in
                                                       MyDCM_inst_CLKIN_IBUFG_INST
    DCM_X1Y1.CLKIN       net (fanout=1)        0.798   MyDCM_inst_CLKIN_IBUFG
    DCM_X1Y1.CLK2X       Tdcmino              -4.186   MyDCM_inst_MyDCM_inst
                                                       MyDCM_inst_MyDCM_inst
    BUFGMUX7P.I0         net (fanout=1)        0.852   MyDCM_inst_CLK2X_BUF
    BUFGMUX7P.O          Tgi0o                 0.589   MyDCM_inst_CLK2X_BUFG_INST
                                                       MyDCM_inst_CLK2X_BUFG_INST.GCLKMUX
                                                       MyDCM_inst_CLK2X_BUFG_INST
    RAMB16_X1Y1.CLKB     net (fanout=27)       0.474   rd_clk
    -------------------------------------------------  ---------------------------
    Total                                     -0.648ns (-2.772ns logic, 2.124ns route)

  Data Path: fifo_2048x8_inst_FIFO_BRAM.B to rd_data<2>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    RAMB16_X1Y1.DOB2     Tbcko                 2.647   fifo_2048x8_inst_FIFO_BRAM
                                                       fifo_2048x8_inst_FIFO_BRAM.B
    D15.O1               net (fanout=1)        1.273   rd_data_2_OBUF
    D15.PAD              Tioop                 6.107   rd_data<2>
                                                       rd_data_2_OBUF
                                                       rd_data<2>
    -------------------------------------------------  ---------------------------
    Total                                     10.027ns (8.754ns logic, 1.273ns route)
                                                       (87.3% logic, 12.7% route)

--------------------------------------------------------------------------------


2 constraints not met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock wr_clk_in
---------------+------------+------------+
               |  Setup to  |  Hold to   |
Source Pad     | clk (edge) | clk (edge) |
---------------+------------+------------+
data_ch        |    1.840(R)|   -0.765(R)|
rd             |    3.690(R)|   -3.007(R)|
reset          |    5.540(R)|   -4.982(R)|
---------------+------------+------------+

Clock wr_clk_in to Pad
---------------+------------+
               | clk (edge) |
Destination Pad|   to PAD   |
---------------+------------+
almost_empty   |    5.873(R)|
almost_full    |    5.882(R)|
empty          |    5.883(R)|
full           |    5.871(R)|
pn_lock_rd_clk |    6.997(R)|
rd_data<0>     |    9.431(R)|
rd_data<1>     |    9.379(R)|
rd_data<2>     |    9.379(R)|
rd_data<3>     |    9.083(R)|
rd_data<4>     |    9.083(R)|
rd_data<5>     |    9.083(R)|
rd_data<6>     |    9.345(R)|
rd_data<7>     |    9.378(R)|
---------------+------------+

Clock to Setup on destination clock wr_clk_in
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
wr_clk_in      |    6.767|         |         |         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 10  Score: 4240

Constraints cover 1152 paths, 0 nets, and 488 connections (90.5% coverage)

Design statistics:
   Minimum period:   6.767ns (Maximum frequency: 147.776MHz)
   Minimum input arrival time before clock:   5.540ns
   Minimum output required time after clock:   9.431ns


Analysis completed Thu Jul 18 14:59:44 2002
--------------------------------------------------------------------------------