ch_fifo.twr

it describe how to develop the field programmable gate array

--------------------------------------------------------------------------------
Release 5.1i - Trace F.22
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Y:/XILI/QualityPartnerBuild3/bin/nt/trce.exe -quiet -e 3 -l 3 -xml ch_fifo
ch_fifo.ncd -o ch_fifo.twr ch_fifo.pcf

Design file:              ch_fifo.ncd
Physical constraint file: ch_fifo.pcf
Device,speed:             xc2v40,-4 (ADVANCED 1.108 2002-06-12, STEPPING level 1)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

WARNING:Timing:2721 - The clock MyDCM_inst_CLKIN_IBUFG is the input to DCM
   MyDCM_inst_MyDCM_inst.  MyDCM_inst_CLKIN_IBUFG has a low pulse width of
   12500 ps and a high pulse width of 12500 ps.  This violates the pulse width
   of MyDCM_inst_MyDCM_inst which has a maximum low pulse width of 1050 ps and
   a maximum high pulse width of 1050 ps.
WARNING:Timing:2721 - The clock MyDCM_inst_CLKIN_IBUFG is the input to DCM
   MyDCM_inst_MyDCM_inst.  MyDCM_inst_CLKIN_IBUFG has a low pulse width of
   12500 ps and a high pulse width of 12500 ps.  This violates the pulse width
   of MyDCM_inst_MyDCM_inst which has a maximum low pulse width of 1050 ps and
   a maximum high pulse width of 1050 ps.

================================================================================
Timing constraint: TS_wr_clk_in = PERIOD TIMEGRP "wr_clk_in"  25 nS   HIGH 50.000000 % ;

 0 items analyzed, 0 timing errors detected.
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_MyDCM_inst_CLK0_BUF = PERIOD TIMEGRP "MyDCM_inst_CLK0_BUF" TS_wr_clk_in * 
1.000000 HIGH 50.000 % ;

 743 items analyzed, 0 timing errors detected.
 Minimum period is   6.767ns.
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_MyDCM_inst_CLK2X_BUF = PERIOD TIMEGRP "MyDCM_inst_CLK2X_BUF" TS_wr_clk_in / 
2.000000 HIGH 50.000 % ;

 381 items analyzed, 0 timing errors detected.
 Minimum period is   6.317ns.
--------------------------------------------------------------------------------

================================================================================
Timing constraint: OFFSET = IN 4.500 nS  BEFORE COMP "wr_clk_in" ;

 15 items analyzed, 2 timing errors detected.
 Minimum allowable offset is   5.540ns.
--------------------------------------------------------------------------------
Slack:                  -1.040ns (requirement - (data path - clock path - clock arrival))
  Source:               reset (PAD)
  Destination:          fifo_2048x8_inst_FIFO_BRAM.A (RAM)
  Destination Clock:    wr_clk rising at 0.000ns
  Requirement:          4.500ns
  Data Path Delay:      4.923ns (Levels of Logic = 1)
  Clock Path Delay:     -0.617ns (Levels of Logic = 3)

  Data Path: reset to fifo_2048x8_inst_FIFO_BRAM.A
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    D12.I                Tiopi                 0.825   reset
                                                       reset
                                                       reset_IBUF
    RAMB16_X1Y1.SSRA     net (fanout=53)       2.448   reset_IBUF
    RAMB16_X1Y1.CLKA     Tbrck                 1.650   fifo_2048x8_inst_FIFO_BRAM
                                                       fifo_2048x8_inst_FIFO_BRAM.A
    -------------------------------------------------  ---------------------------
    Total                                      4.923ns (2.475ns logic, 2.448ns route)
                                                       (50.3% logic, 49.7% route)

  Clock Path: wr_clk_in to fifo_2048x8_inst_FIFO_BRAM.A
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    A8.I                 Tiopi                 0.783   wr_clk_in
                                                       wr_clk_in
                                                       MyDCM_inst_CLKIN_IBUFG_INST
    DCM_X1Y1.CLKIN       net (fanout=1)        0.758   MyDCM_inst_CLKIN_IBUFG
    DCM_X1Y1.CLK0        Tdcmino              -3.976   MyDCM_inst_MyDCM_inst
                                                       MyDCM_inst_MyDCM_inst
    BUFGMUX5P.I0         net (fanout=1)        0.809   MyDCM_inst_CLK0_BUF
    BUFGMUX5P.O          Tgi0o                 0.559   MyDCM_inst_CLK0_BUFG_INST
                                                       MyDCM_inst_CLK0_BUFG_INST.GCLKMUX
                                                       MyDCM_inst_CLK0_BUFG_INST
    RAMB16_X1Y1.CLKA     net (fanout=27)       0.450   wr_clk
    -------------------------------------------------  ---------------------------
    Total                                     -0.617ns (-2.634ns logic, 2.017ns route)

--------------------------------------------------------------------------------
Slack:                  -1.039ns (requirement - (data path - clock path - clock arrival))
  Source:               reset (PAD)
  Destination:          fifo_2048x8_inst_FIFO_BRAM.B (RAM)
  Destination Clock:    rd_clk rising at 0.000ns
  Requirement:          4.500ns
  Data Path Delay:      4.922ns (Levels of Logic = 1)
  Clock Path Delay:     -0.617ns (Levels of Logic = 3)

  Data Path: reset to fifo_2048x8_inst_FIFO_BRAM.B
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    D12.I                Tiopi                 0.825   reset
                                                       reset
                                                       reset_IBUF
    RAMB16_X1Y1.SSRB     net (fanout=53)       2.447   reset_IBUF
    RAMB16_X1Y1.CLKB     Tbrck                 1.650   fifo_2048x8_inst_FIFO_BRAM
                                                       fifo_2048x8_inst_FIFO_BRAM.B
    -------------------------------------------------  ---------------------------
    Total                                      4.922ns (2.475ns logic, 2.447ns route)
                                                       (50.3% logic, 49.7% route)

  Clock Path: wr_clk_in to fifo_2048x8_inst_FIFO_BRAM.B
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    A8.I                 Tiopi                 0.783   wr_clk_in
                                                       wr_clk_in
                                                       MyDCM_inst_CLKIN_IBUFG_INST
    DCM_X1Y1.CLKIN       net (fanout=1)        0.758   MyDCM_inst_CLKIN_IBUFG
    DCM_X1Y1.CLK2X       Tdcmino              -3.976   MyDCM_inst_MyDCM_inst
                                                       MyDCM_inst_MyDCM_inst
    BUFGMUX7P.I0         net (fanout=1)        0.809   MyDCM_inst_CLK2X_BUF
    BUFGMUX7P.O          Tgi0o                 0.559   MyDCM_inst_CLK2X_BUFG_INST
                                                       MyDCM_inst_CLK2X_BUFG_INST.GCLKMUX
                                                       MyDCM_inst_CLK2X_BUFG_INST
    RAMB16_X1Y1.CLKB     net (fanout=27)       0.450   rd_clk
    -------------------------------------------------  ---------------------------
    Total                                     -0.617ns (-2.634ns logic, 2.017ns route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: OFFSET = OUT 9 nS  AFTER COMP "wr_clk_in" ;

 13 items analyzed, 8 timing errors detected.
 Minimum allowable offset is   9.431ns.
--------------------------------------------------------------------------------
Slack:                  -0.431ns (requirement - (clock arrival + clock path + data path))
  Source:               wr_clk_in (PAD)
  Destination:          rd_data<0> (PAD)
  Source Clock:         rd_clk rising at 0.000ns
  Requirement:          9.000ns
  Data Path Delay:      10.079ns (Levels of Logic = 1)
  Clock Path Delay:     -0.648ns (Levels of Logic = 3)

  Clock Path: wr_clk_in to fifo_2048x8_inst_FIFO_BRAM.B
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    A8.I                 Tiopi                 0.825   wr_clk_in
                                                       wr_clk_in
                                                       MyDCM_inst_CLKIN_IBUFG_INST
    DCM_X1Y1.CLKIN       net (fanout=1)        0.798   MyDCM_inst_CLKIN_IBUFG
    DCM_X1Y1.CLK2X       Tdcmino              -4.186   MyDCM_inst_MyDCM_inst
                                                       MyDCM_inst_MyDCM_inst
    BUFGMUX7P.I0         net (fanout=1)        0.852   MyDCM_inst_CLK2X_BUF
    BUFGMUX7P.O          Tgi0o                 0.589   MyDCM_inst_CLK2X_BUFG_INST
                                                       MyDCM_inst_CLK2X_BUFG_INST.GCLKMUX
                                                       MyDCM_inst_CLK2X_BUFG_INST