ch_fifo.tw1

it describe how to develop the field programmable gate array

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Release 5.1i - Trace F.22
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Y:/XILI/QualityPartnerBuild3/bin/nt/trce.exe -quiet -e 3 -l 3 -s -4 -xml
ch_fifo_preroute ch_fifo_map.ncd -o ch_fifo_preroute.twr ch_fifo.pcf

Design file:              ch_fifo_map.ncd
Physical constraint file: ch_fifo.pcf
Device,speed:             xc2v40,-4 (ADVANCED 1.108 2002-06-12, STEPPING level 1)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

WARNING:Timing:2721 - The clock MyDCM_inst_CLKIN_IBUFG is the input to DCM
   MyDCM_inst_MyDCM_inst.  MyDCM_inst_CLKIN_IBUFG has a low pulse width of
   12500 ps and a high pulse width of 12500 ps.  This violates the pulse width
   of MyDCM_inst_MyDCM_inst which has a maximum low pulse width of 1050 ps and
   a maximum high pulse width of 1050 ps.
WARNING:Timing:2721 - The clock MyDCM_inst_CLKIN_IBUFG is the input to DCM
   MyDCM_inst_MyDCM_inst.  MyDCM_inst_CLKIN_IBUFG has a low pulse width of
   12500 ps and a high pulse width of 12500 ps.  This violates the pulse width
   of MyDCM_inst_MyDCM_inst which has a maximum low pulse width of 1050 ps and
   a maximum high pulse width of 1050 ps.

================================================================================
Timing constraint: TS_wr_clk_in = PERIOD TIMEGRP "wr_clk_in"  25 nS   HIGH 50.000000 % ;

 0 items analyzed, 0 timing errors detected.
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================================================================================
Timing constraint: TS_MyDCM_inst_CLK0_BUF = PERIOD TIMEGRP "MyDCM_inst_CLK0_BUF" TS_wr_clk_in * 
1.000000 HIGH 50.000 % ;

 743 items analyzed, 0 timing errors detected.
 Minimum period is   4.593ns.
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_MyDCM_inst_CLK2X_BUF = PERIOD TIMEGRP "MyDCM_inst_CLK2X_BUF" TS_wr_clk_in / 
2.000000 HIGH 50.000 % ;

 381 items analyzed, 0 timing errors detected.
 Minimum period is   4.593ns.
--------------------------------------------------------------------------------

================================================================================
Timing constraint: OFFSET = IN 4.500 nS  BEFORE COMP "wr_clk_in" ;

 15 items analyzed, 0 timing errors detected.
 Minimum allowable offset is   3.458ns.
--------------------------------------------------------------------------------

================================================================================
Timing constraint: OFFSET = OUT 9 nS  AFTER COMP "wr_clk_in" ;

 13 items analyzed, 0 timing errors detected.
 Minimum allowable offset is   7.920ns.
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All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock wr_clk_in
---------------+------------+------------+
               |  Setup to  |  Hold to   |
Source Pad     | clk (edge) | clk (edge) |
---------------+------------+------------+
data_ch        |    1.938(R)|   -1.717(R)|
rd             |    3.004(R)|   -2.447(R)|
reset          |    3.458(R)|   -3.043(R)|
---------------+------------+------------+

Clock wr_clk_in to Pad
---------------+------------+
               | clk (edge) |
Destination Pad|   to PAD   |
---------------+------------+
almost_empty   |    5.582(R)|
almost_full    |    5.582(R)|
empty          |    5.582(R)|
full           |    5.582(R)|
pn_lock_rd_clk |    5.841(R)|
rd_data<0>     |    7.920(R)|
rd_data<1>     |    7.920(R)|
rd_data<2>     |    7.920(R)|
rd_data<3>     |    7.920(R)|
rd_data<4>     |    7.920(R)|
rd_data<5>     |    7.920(R)|
rd_data<6>     |    7.920(R)|
rd_data<7>     |    7.920(R)|
---------------+------------+

Clock to Setup on destination clock wr_clk_in
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
wr_clk_in      |    4.593|         |         |         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 1152 paths, 0 nets, and 488 connections (90.5% coverage)

Design statistics:
   Minimum period:   4.593ns (Maximum frequency: 217.723MHz)
   Minimum input arrival time before clock:   3.458ns
   Minimum output required time after clock:   7.920ns


Analysis completed Thu Jul 18 14:55:28 2002
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