ch_fifo.pcf

it describe how to develop the field programmable gate array

SCHEMATIC START ;
// created by map version F.22 on Thu Jul 18 14:55:23 2002 
COMP "fifo_2048x8_inst_FIFO_BRAM" LOCATE =  SITE "RAMB16_X1Y1" LEVEL 1; 
COMP "rd_data<7>" LOCATE =  SITE "BANK2" LEVEL 1; 
COMP "rd_data<0>" LOCATE =  SITE "BANK2" LEVEL 1; 
COMP "rd_data<1>" LOCATE =  SITE "BANK2" LEVEL 1; 
COMP "rd_data<2>" LOCATE =  SITE "BANK2" LEVEL 1; 
COMP "rd_data<3>" LOCATE =  SITE "BANK2" LEVEL 1; 
COMP "rd_data<4>" LOCATE =  SITE "BANK2" LEVEL 1; 
COMP "rd_data<5>" LOCATE =  SITE "BANK2" LEVEL 1; 
COMP "rd_data<6>" LOCATE =  SITE "BANK2" LEVEL 1; 
COMP "MyDCM_inst_MyDCM_inst" LOCATE =  SITE "DCM_X1Y1" LEVEL 1; 
PIN "fifo_2048x8_inst_FIFO_BRAM.A_pins<53>" = NET "wr_clk" BEL 
"fifo_2048x8_inst_FIFO_BRAM.A" ;
TIMEGRP "MyDCM_inst_CLK0_BUF" = BEL 
"pn_correlator_inst_pn_correlation_inst_sr_data_3" PIN 
"fifo_2048x8_inst_FIFO_BRAM.A_pins<53>" BEL 
"pn_correlator_inst_pn_correlation_inst_sr_data_5" BEL 
"pn_correlator_inst_pn_correlation_inst_sr_data_6" BEL 
"pn_correlator_inst_pn_correlation_inst_sr_data_0" BEL 
"pn_correlator_inst_pn_correlation_inst_sr_data_4" BEL 
"pn_correlator_inst_pn_correlation_inst_sr_data_7" BEL 
"pn_correlator_inst_pn_correlation_inst_sr_data_1" BEL 
"pn_correlator_inst_pn_correlation_inst_sr_data_2" BEL 
"fifo_status_inst_wr_addr_19" BEL "fifo_status_inst_wr_addr_18" BEL 
"fifo_status_inst_wr_addr_20" BEL "fifo_status_inst_wr_addr_21" BEL 
"fifo_status_inst_wr_addr_11" BEL "fifo_status_inst_wr_addr_12" BEL 
"fifo_status_inst_wr_addr_13" BEL "fifo_status_inst_wr_addr_14" BEL 
"fifo_status_inst_wr_addr_15" BEL "fifo_status_inst_wr_addr_16" BEL 
"fifo_status_inst_wr_addr_17" BEL 
"pn_correlator_inst_pn_correlation_fsm_inst_eight_cnt_1" BEL 
"pn_correlator_inst_pn_correlation_fsm_inst_eight_cnt_0" BEL 
"pn_correlator_inst_pn_correlation_fsm_inst_pn_addr_cntr_9" BEL 
"pn_correlator_inst_pn_correlation_fsm_inst_pn_addr_cntr_8" BEL 
"pn_correlator_inst_pn_correlation_fsm_inst_pn_addr_cntr_7" BEL 
"pn_correlator_inst_pn_correlation_fsm_inst_pn_addr_cntr_6" BEL 
"pn_correlator_inst_pn_correlation_fsm_inst_pn_addr_cntr_5" BEL 
"pn_correlator_inst_pn_correlation_fsm_inst_pn_addr_cntr_4" BEL 
"pn_correlator_inst_pn_correlation_fsm_inst_pn_addr_cntr_3" BEL 
"pn_correlator_inst_pn_correlation_fsm_inst_pn_addr_cntr_2" BEL 
"pn_correlator_inst_pn_correlation_fsm_inst_pn_addr_cntr_1" BEL 
"pn_correlator_inst_pn_correlation_fsm_inst_pn_addr_cntr_0" BEL 
"pn_correlator_inst_pn_correlation_fsm_inst_cs_1" BEL 
"pn_correlator_inst_pn_correlation_fsm_inst_eight_cnt_2" BEL 
"pn_correlator_inst_pn_correlation_fsm_inst_pn_addr_cntr_10" BEL 
"pn_correlator_inst_pn_correlation_fsm_inst_pn_acq" BEL 
"pn_correlator_inst_pn_correlation_fsm_inst_pn_acq_q0" BEL 
"pn_correlator_inst_pn_correlation_fsm_inst_wr" BEL 
"pn_correlator_inst_pn_correlation_fsm_inst_cs_3" BEL 
"pn_correlator_inst_pn_correlation_fsm_inst_cs_2" BEL 
"pn_correlator_inst_pn_correlation_fsm_inst_cs_0" ;
PIN "fifo_2048x8_inst_FIFO_BRAM.B_pins<53>" = NET "rd_clk" BEL 
"fifo_2048x8_inst_FIFO_BRAM.B" ;
TIMEGRP "MyDCM_inst_CLK2X_BUF" = PIN "fifo_2048x8_inst_FIFO_BRAM.B_pins<53>" 
BEL "fifo_status_inst_flag_cnt_9" BEL "fifo_status_inst_flag_cnt_8" BEL 
"fifo_status_inst_flag_cnt_7" BEL "fifo_status_inst_flag_cnt_6" BEL 
"fifo_status_inst_flag_cnt_5" BEL "fifo_status_inst_flag_cnt_4" BEL 
"fifo_status_inst_pn_lock_rd_clk_p0" BEL "fifo_status_inst_pn_lock_rd_clk" BEL 
"fifo_status_inst_rd_addr_9" BEL "fifo_status_inst_wr_dtct_3" BEL 
"fifo_status_inst_flag_wr_addr_10" BEL "fifo_status_inst_flag_cnt_10" BEL 
"fifo_status_inst_full" BEL "fifo_status_inst_almost_full" BEL 
"fifo_status_inst_empty" BEL "fifo_status_inst_almost_empty" BEL 
"fifo_status_inst_wr_dtct_0" BEL "fifo_status_inst_wr_dtct_1" BEL 
"fifo_status_inst_wr_dtct_2" BEL "fifo_status_inst_flag_wr_addr_0" BEL 
"fifo_status_inst_flag_wr_addr_1" BEL "fifo_status_inst_flag_wr_addr_2" BEL 
"fifo_status_inst_flag_wr_addr_3" BEL "fifo_status_inst_flag_wr_addr_4" BEL 
"fifo_status_inst_flag_wr_addr_5" BEL "fifo_status_inst_flag_wr_addr_6" BEL 
"fifo_status_inst_flag_wr_addr_7" BEL "fifo_status_inst_flag_wr_addr_8" BEL 
"fifo_status_inst_flag_wr_addr_9" BEL "fifo_status_inst_flag_cnt_0" BEL 
"fifo_status_inst_flag_cnt_1" BEL "fifo_status_inst_flag_cnt_2" BEL 
"fifo_status_inst_flag_cnt_3" BEL "fifo_status_inst_rd_addr_10" BEL 
"fifo_status_inst_rd_addr_0" BEL "fifo_status_inst_rd_addr_1" BEL 
"fifo_status_inst_rd_addr_2" BEL "fifo_status_inst_rd_addr_3" BEL 
"fifo_status_inst_rd_addr_4" BEL "fifo_status_inst_rd_addr_5" BEL 
"fifo_status_inst_rd_addr_6" BEL "fifo_status_inst_rd_addr_7" BEL 
"fifo_status_inst_rd_addr_8" ;
TIMEGRP "wr_clk_in" = BEL "MyDCM_inst_MyDCM_inst" ; 
TS_wr_clk_in = PERIOD TIMEGRP "wr_clk_in"  25 nS   HIGH 50.000000 % ;
TS_MyDCM_inst_CLK0_BUF = PERIOD TIMEGRP "MyDCM_inst_CLK0_BUF" TS_wr_clk_in * 
1.000000 HIGH 50.000 % ;
TS_MyDCM_inst_CLK2X_BUF = PERIOD TIMEGRP "MyDCM_inst_CLK2X_BUF" TS_wr_clk_in / 
2.000000 HIGH 50.000 % ;
OFFSET = IN 4.500 nS  BEFORE COMP "wr_clk_in" ;
OFFSET = OUT 9 nS  AFTER COMP "wr_clk_in" ;
SCHEMATIC END ;