myucf.ucf

it describe how to develop the field programmable gate array

#PACE: Start of Constraints extracted by PACE from the Design
INST "inst_mydcm_dcm_inst" LOC = "DCM_X1Y1"  ;
INST "fifo_2048x8_inst_fifo_bram" LOC = "RAMB16_X1Y1";
NET "rd_data<0>" LOC = "BANK2";
NET "rd_data<1>" LOC = "BANK2";
NET "rd_data<2>" LOC = "BANK2";
NET "rd_data<3>" LOC = "BANK2";
NET "rd_data<4>" LOC = "BANK2";
NET "rd_data<5>" LOC = "BANK2";
NET "rd_data<6>" LOC = "BANK2";
NET "rd_data<7>" LOC = "BANK2";
NET "wr_clk_in" TNM_NET = "wr_clk_in";