ch_fifo.syr

it describe how to develop the field programmable gate array

WARNING:Xst:1290 - Hierarchical block <I27> is unconnected in block <Mmux__n0011>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <I28> is unconnected in block <Mmux__n0011>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <I29> is unconnected in block <Mmux__n0011>.
   It will be removed from the design.

Optimizing unit <ch_fifo> ...

Optimizing unit <fifo_status> ...

Optimizing unit <pn_correlation> ...

Optimizing unit <pn_correlation_fsm> ...

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <fifo_status_inst_half_full> is unconnected in block <ch_fifo>.
Loading device for application Xst from file '2v40.nph' in environment Y:/XILI/QualityPartnerBuild3.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block ch_fifo, actual ratio is 59.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Output File Name               : ch_fifo.ngr
Top Level Output File Name         : ch_fifo
Output Format                      : NGC
Optimization Criterion             : Speed
Keep Hierarchy                     : NO
Macro Generator                    : macro+

Design Statistics
# IOs                              : 17

Macro Statistics :
# Registers                        : 28
#      1-bit register              : 23
#      11-bit register             : 3
#      3-bit register              : 1
#      4-bit register              : 1
# Counters                         : 2
#      11-bit up counter           : 2
# Adders/Subtractors               : 19
#      11-bit adder                : 1
#      11-bit subtractor           : 1
#      32-bit adder                : 10
#      32-bit subtractor           : 1
#      33-bit adder                : 6
# Comparators                      : 3
#      11-bit comparator greatequal: 2
#      11-bit comparator lessequal : 1

Cell Usage :
# BELS                             : 436
#      GND                         : 1
#      LUT1                        : 12
#      LUT2                        : 33
#      LUT2_D                      : 3
#      LUT2_L                      : 2
#      LUT3                        : 46
#      LUT3_D                      : 16
#      LUT3_L                      : 24
#      LUT4                        : 62
#      LUT4_D                      : 9
#      LUT4_L                      : 21
#      MUXCY                       : 88
#      MUXF5                       : 3
#      VCC                         : 1
#      XORCY                       : 115
# FlipFlops/Latches                : 84
#      FDC                         : 50
#      FDCE                        : 11
#      FDCPE                       : 22
#      FDP                         : 1
# RAMS                             : 1
#      ramb16_s9_s9                : 1
# Clock Buffers                    : 2
#      bufg                        : 2
# IO Buffers                       : 17
#      IBUF                        : 3
#      ibufg                       : 1
#      OBUF                        : 13
# DCMs                             : 1
#      dcm                         : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2v40fg256-4 

 Number of Slices:                     131  out of    256    51%  
 Number of Slice Flip Flops:            84  out of    512    16%  
 Number of 4 input LUTs:               228  out of    512    44%  
 Number of bonded IOBs:                 17  out of     88    19%  
 Number of BRAMs:                        1  out of      4    25%  
 Number of GCLKs:                        2  out of     16    12%  
 Number of DCMs:                         1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
wr_clk_in                          | inst_mydcm_dcm_inst:clk0| 41    |
wr_clk_in                          | inst_mydcm_dcm_inst:clk2x| 44    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 21.626ns (Maximum Frequency: 46.241MHz)
   Minimum input arrival time before clock: 4.770ns
   Maximum output required time after clock: 9.114ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'wr_clk_in'
Delay:               21.626ns (Levels of Logic = 22)
  Source:            pn_correlator_inst_pn_correlation_inst_sr_data_1
  Destination:       pn_correlator_inst_pn_correlation_inst_pn_fnd
  Source Clock:      wr_clk_in rising
  Destination Clock: wr_clk_in rising

  Data Path: pn_correlator_inst_pn_correlation_inst_sr_data_1 to pn_correlator_inst_pn_correlation_inst_pn_fnd
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:c->q             22   0.568   2.052  pn_correlator_inst_pn_correlation_inst_sr_data_1 (pn_correlator_inst_pn_correlation_inst_sr_data_1)
     LUT3_L:I0->LO         0   0.439   0.000  pn_correlator_inst_pn_correlation_inst_madd__n0048_inst_cy_67 (pn_correlator_inst_pn_correlation_inst_madd__n0048_inst_cy_67)
     XORCY:ci->o           3   1.274   0.981  pn_correlator_inst_pn_correlation_inst_madd__n0048_inst_sum_66 (pn_correlator_inst_pn_correlation_inst__n0103<1>)
     LUT3:i2->o            3   0.439   0.000  pn_correlator_inst_pn_correlation_inst_mmux__n0013_i30_result1 (pn_correlator_inst_pn_correlation_inst__n0013<1>)
     MUXCY:s->o            0   0.298   0.000  pn_correlator_inst_pn_correlation_inst_madd__n0053_inst_cy_68 (pn_correlator_inst_pn_correlation_inst_madd__n0053_inst_cy_68)
     XORCY:ci->o           3   1.274   0.981  pn_correlator_inst_pn_correlation_inst_madd__n0053_inst_sum_67 (pn_correlator_inst_pn_correlation_inst__n0107<2>)
     LUT4:i2->o            1   0.439   0.000  pn_correlator_inst_pn_correlation_inst_madd__n0058_inst_cy_69 (pn_correlator_inst_pn_correlation_inst_madd__n0058_inst_cy_69)
     XORCY:ci->o           1   1.274   0.408  pn_correlator_inst_pn_correlation_inst_madd__n0058_inst_sum_68 (pn_correlator_inst_pn_correlation_inst__n0111<3>)
     LUT3_L:I1->LO         1   0.439   0.000  pn_correlator_inst_pn_correlation_inst_mmux__n0021_i28_result1 (pn_correlator_inst_pn_correlation_inst__n0021<3>)
     MUXCY:s->o            2   0.298   0.000  pn_correlator_inst_pn_correlation_inst_madd__n0038_inst_cy_70 (pn_correlator_inst_pn_correlation_inst_madd__n0038_inst_cy_70)
     XORCY:ci->o           1   1.274   0.408  pn_correlator_inst_pn_correlation_inst_madd__n0038_inst_sum_69 (pn_correlator_inst_pn_correlation_inst__n0115<4>)
     LUT4_D:I3->O          2   0.439   0.000  pn_correlator_inst_pn_correlation_inst_mmux__n0025_i27_result11 (n17220)
     MUXCY:s->o            1   0.298   0.000  pn_correlator_inst_pn_correlation_inst_madd__n0071_inst_cy_71 (pn_correlator_inst_pn_correlation_inst_madd__n0071_inst_cy_71)
     XORCY:ci->o           1   1.274   0.408  pn_correlator_inst_pn_correlation_inst_madd__n0071_inst_sum_70 (pn_correlator_inst_pn_correlation_inst__n0071<5>)
     LUT4:i1->o            1   0.439   0.408  pn_correlator_inst_pn_correlation_inst__n0028<5>1 (pn_correlator_inst_pn_correlation_inst__n0028<5>)
     LUT4_L:I0->LO         1   0.439   0.000  pn_correlator_inst_pn_correlation_inst_msub__n0078_inst_lut2_161 (pn_correlator_inst_pn_correlation_inst_msub__n0078_inst_lut2_16)
     MUXCY:s->o            1   0.298   0.000  pn_correlator_inst_pn_correlation_inst_msub__n0078_inst_cy_40 (pn_correlator_inst_pn_correlation_inst_msub__n0078_inst_cy_40)
     MUXCY:ci->o           0   0.053   0.000  pn_correlator_inst_pn_correlation_inst_msub__n0078_inst_cy_41 (pn_correlator_inst_pn_correlation_inst_msub__n0078_inst_cy_41)
     XORCY:ci->o           1   1.274   0.408  pn_correlator_inst_pn_correlation_inst_msub__n0078_inst_sum_44 (pn_correlator_inst_pn_correlation_inst__n0078<11>)
     LUT4:i1->o            1   0.439   0.408  pn_correlator_inst_pn_correlation_inst__n007483 (choice181)
     LUT4_L:I3->LO         1   0.439   0.100  pn_correlator_inst_pn_correlation_inst__n0074140 (choice184)
     LUT3:i0->o            1   0.439   0.408  pn_correlator_inst_pn_correlation_inst__n0074207 (choice198)
     LUT3_L:I0->LO         1   0.439   0.000  pn_correlator_inst_pn_correlation_inst__n0074333 (pn_correlator_inst_pn_correlation_inst__n0074)
     FDC:d                     0.370          pn_correlator_inst_pn_correlation_inst_pn_fnd
    ----------------------------------------
    Total                     21.626ns (14.656ns logic, 6.970ns route)
                                       (67.8% logic, 32.2% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'wr_clk_in'
Offset:              4.770ns (Levels of Logic = 1)
  Source:            reset
  Destination:       fifo_2048x8_inst_fifo_bram
  Destination Clock: wr_clk_in rising 2.0X

  Data Path: reset to fifo_2048x8_inst_fifo_bram
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:i->o            86   0.825   2.295  reset_ibuf (reset_ibuf)
     ramb16_s9_s9:ssra         1.650          fifo_2048x8_inst_fifo_bram
    ----------------------------------------
    Total                      4.770ns (2.475ns logic, 2.295ns route)
                                       (51.9% logic, 48.1% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'wr_clk_in'
Offset:              9.114ns (Levels of Logic = 1)
  Source:            fifo_2048x8_inst_fifo_bram
  Destination:       rd_data<2>
  Source Clock:      wr_clk_in rising 2.0X

  Data Path: fifo_2048x8_inst_fifo_bram to rd_data<2>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     ramb16_s9_s9:clkb->dob2    1   2.599   0.408  fifo_2048x8_inst_fifo_bram (rd_data_2_obuf)
     OBUF:i->o                 6.107          rd_data_2_obuf (rd_data<2>)
    ----------------------------------------
    Total                      9.114ns (8.706ns logic, 0.408ns route)
                                       (95.5% logic, 4.5% route)

=========================================================================
CPU : 15.58 / 20.50 s | Elapsed : 15.00 / 20.00 s
 
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Total memory usage is 74492 kilobytes