ch_fifo.syr

it describe how to develop the field programmable gate array

Release 5.1i - xst F.22
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
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--> Reading design: ch_fifo.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Low Level Synthesis
  6) Final Report
     6.1) Device utilization summary
     6.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : ch_fifo.prj
Input Format                       : VHDL
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : ch_fifo
Output Format                      : NGC
Target Device                      : xc2v40-4fg256

---- Source Options
Entity Name                        : ch_fifo
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : lower
Top module area constraint         : 100
Top module allowed area overflow   : 5

---- Other Options
read_cores                         : YES
cross_clock_analysis               : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file W:/marial/v5/labs/flow/./vhdl/ch_fifo_pack.vhd in Library work.
Architecture ch_fifo_pack of Entity ch_fifo_pack is up to date.
Compiling vhdl file W:/marial/v5/labs/flow/./vhdl/pn_correlation.vhd in Library work.
Architecture rtl of Entity pn_correlation is up to date.
Compiling vhdl file W:/marial/v5/labs/flow/./vhdl/pn_correlation_fsm.vhd in Library work.
Architecture rtl of Entity pn_correlation_fsm is up to date.
Compiling vhdl file W:/marial/v5/labs/flow/MyDCM.vhd in Library work.
Architecture struct of Entity mydcm is up to date.
Compiling vhdl file W:/marial/v5/labs/flow/./vhdl/pn_correlator.vhd in Library work.
Architecture structure of Entity pn_correlator is up to date.
Compiling vhdl file W:/marial/v5/labs/flow/./vhdl/fifo_status.vhd in Library work.
Architecture rtl of Entity fifo_status is up to date.
Compiling vhdl file W:/marial/v5/labs/flow/./vhdl/fifo_2048x8.vhd in Library work.
Architecture structure of Entity fifo_2048x8 is up to date.
Compiling vhdl file W:/marial/v5/labs/flow/./vhdl/ch_fifo.vhd in Library work.
Entity <ch_fifo> (Architecture <structure>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================

Analyzing Entity <ch_fifo> (Architecture <structure>).
WARNING:Xst:753 - W:/marial/v5/labs/flow/./vhdl/ch_fifo.vhd line 77: Unconnected output port 'half_full' of component 'fifo_status'.
Entity <ch_fifo> analyzed. Unit <ch_fifo> generated.

Analyzing Entity <mydcm> (Architecture <struct>).
WARNING:Xst:753 - W:/marial/v5/labs/flow/MyDCM.vhd line 113: Unconnected output port 'clk90' of component 'dcm'.
WARNING:Xst:753 - W:/marial/v5/labs/flow/MyDCM.vhd line 113: Unconnected output port 'clk180' of component 'dcm'.
WARNING:Xst:753 - W:/marial/v5/labs/flow/MyDCM.vhd line 113: Unconnected output port 'clk270' of component 'dcm'.
WARNING:Xst:753 - W:/marial/v5/labs/flow/MyDCM.vhd line 113: Unconnected output port 'clkdv' of component 'dcm'.
WARNING:Xst:753 - W:/marial/v5/labs/flow/MyDCM.vhd line 113: Unconnected output port 'clk2x180' of component 'dcm'.
WARNING:Xst:753 - W:/marial/v5/labs/flow/MyDCM.vhd line 113: Unconnected output port 'clkfx' of component 'dcm'.
WARNING:Xst:753 - W:/marial/v5/labs/flow/MyDCM.vhd line 113: Unconnected output port 'clkfx180' of component 'dcm'.
WARNING:Xst:753 - W:/marial/v5/labs/flow/MyDCM.vhd line 113: Unconnected output port 'status' of component 'dcm'.
WARNING:Xst:753 - W:/marial/v5/labs/flow/MyDCM.vhd line 113: Unconnected output port 'psdone' of component 'dcm'.
WARNING:Xst:766 - W:/marial/v5/labs/flow/MyDCM.vhd line 113: Generating a Black Box for component <dcm>.
    Set user-defined property "CLK_FEEDBACK =  1X" for instance <dcm_inst> in unit <mydcm>.
    Set user-defined property "CLKDV_DIVIDE =  2.000000" for instance <dcm_inst> in unit <mydcm>.
    Set user-defined property "CLKFX_DIVIDE =  1" for instance <dcm_inst> in unit <mydcm>.
    Set user-defined property "CLKFX_MULTIPLY =  4" for instance <dcm_inst> in unit <mydcm>.
    Set user-defined property "CLKIN_DIVIDE_BY_2 =  false" for instance <dcm_inst> in unit <mydcm>.
    Set user-defined property "CLKIN_PERIOD =  10.000000" for instance <dcm_inst> in unit <mydcm>.
    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <dcm_inst> in unit <mydcm>.
    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <dcm_inst> in unit <mydcm>.
    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <dcm_inst> in unit <mydcm>.
    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <dcm_inst> in unit <mydcm>.
    Set user-defined property "DUTY_CYCLE_CORRECTION =  true" for instance <dcm_inst> in unit <mydcm>.
    Set user-defined property "PHASE_SHIFT =  0" for instance <dcm_inst> in unit <mydcm>.
    Set user-defined property "STARTUP_WAIT =  false" for instance <dcm_inst> in unit <mydcm>.
WARNING:Xst:766 - W:/marial/v5/labs/flow/MyDCM.vhd line 142: Generating a Black Box for component <ibufg>.
WARNING:Xst:766 - W:/marial/v5/labs/flow/MyDCM.vhd line 147: Generating a Black Box for component <bufg>.
WARNING:Xst:766 - W:/marial/v5/labs/flow/MyDCM.vhd line 152: Generating a Black Box for component <bufg>.
Entity <mydcm> analyzed. Unit <mydcm> generated.

Analyzing generic Entity <pn_correlator> (Architecture <structure>).
	k = 10001101
Entity <pn_correlator> analyzed. Unit <pn_correlator> generated.

Analyzing Entity <fifo_status> (Architecture <rtl>).
Entity <fifo_status> analyzed. Unit <fifo_status> generated.

Analyzing Entity <fifo_2048x8> (Architecture <structure>).
WARNING:Xst:753 - W:/marial/v5/labs/flow/./vhdl/fifo_2048x8.vhd line 40: Unconnected output port 'doa' of component 'ramb16_s9_s9'.
WARNING:Xst:753 - W:/marial/v5/labs/flow/./vhdl/fifo_2048x8.vhd line 40: Unconnected output port 'dopa' of component 'ramb16_s9_s9'.
WARNING:Xst:753 - W:/marial/v5/labs/flow/./vhdl/fifo_2048x8.vhd line 40: Unconnected output port 'dopb' of component 'ramb16_s9_s9'.
WARNING:Xst:766 - W:/marial/v5/labs/flow/./vhdl/fifo_2048x8.vhd line 40: Generating a Black Box for component <ramb16_s9_s9>.
Entity <fifo_2048x8> analyzed. Unit <fifo_2048x8> generated.

Analyzing generic Entity <pn_correlation> (Architecture <rtl>).
	k = 10001101
Entity <pn_correlation> analyzed. Unit <pn_correlation> generated.

Analyzing Entity <pn_correlation_fsm> (Architecture <rtl>).
Entity <pn_correlation_fsm> analyzed. Unit <pn_correlation_fsm> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <pn_correlation_fsm>.
    Related source file is W:/marial/v5/labs/flow/./vhdl/pn_correlation_fsm.vhd.
    Using one-hot encoding for signal <cs>.
    Using one-hot encoding for signal <ns>.
    Found 1-bit register for signal <wr>.
    Found 3-bit adder for signal <$n0030> created at line 85.
    Found 11-bit adder for signal <$n0031> created at line 107.
    Found 4-bit register for signal <cs>.
    Found 3-bit register for signal <eight_cnt>.
    Found 1-bit register for signal <pn_acq_i>.
    Found 1-bit register for signal <pn_acq_q0>.
    Found 11-bit register for signal <pn_addr_cntr>.
    Summary:
	inferred  17 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
Unit <pn_correlation_fsm> synthesized.


Synthesizing Unit <pn_correlation>.
    Related source file is W:/marial/v5/labs/flow/./vhdl/pn_correlation.vhd.
    Found 1-bit register for signal <pn_fnd>.
    Found 2-bit adder for signal <$n0034> created at line 60.
    Found 2-bit adder for signal <$n0035> created at line 62.
    Found 32-bit adder for signal <$n0037> created at line 60.
    Found 32-bit adder for signal <$n0038> created at line 62.
    Found 32-bit adder for signal <$n0047> created at line 60.
    Found 32-bit adder for signal <$n0048> created at line 62.
    Found 33-bit adder for signal <$n0049> created at line 62.
    Found 33-bit adder for signal <$n0050> created at line 60.
    Found 32-bit adder for signal <$n0052> created at line 60.
    Found 32-bit adder for signal <$n0053> created at line 62.
    Found 33-bit adder for signal <$n0054> created at line 62.
    Found 33-bit adder for signal <$n0055> created at line 60.
    Found 32-bit adder for signal <$n0057> created at line 60.
    Found 32-bit adder for signal <$n0058> created at line 62.
    Found 33-bit adder for signal <$n0059> created at line 62.
    Found 33-bit adder for signal <$n0060> created at line 60.
    Found 32-bit adder for signal <$n0071> created at line 62.
    Found 32-bit adder for signal <$n0073> created at line 60.
    Found 32-bit subtractor for signal <$n0078> created at line 66.
    Found 1-bit adder carry out for signal <$n0079> created at line 62.
    Found 1-bit adder carry out for signal <$n0080> created at line 60.
    Found 8-bit register for signal <sr_data>.
    Found 584 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   9 D-type flip-flop(s).
	inferred  21 Adder/Subtracter(s).