fifo_2048x8.vhd

来自「it describe how to develop the field pro」· VHDL 代码 · 共 63 行

library ieee;
use ieee.std_logic_1164.all;
-- synopsys translate_off
library unisim;
use unisim.vpkg.all;
use unisim.vcomponents.all;
-- synopsys translate_on

entity fifo_2048x8 is
    
    port (
        rd_clk, wr_clk, wr, rd, reset : in  std_logic;
        wr_addr, rd_addr              : in  std_logic_vector(10 downto 0);
        wr_data                       : in  std_logic_vector (7 downto 0);
        rd_data                       : out std_logic_vector (7 downto 0));

end fifo_2048x8;

architecture structure of fifo_2048x8 is
    component ramb16_s9_s9
        port (
            wea, ena, ssra, clka       : in  std_logic;
            dipa                       : in  std_logic_vector (0 downto 0);
            addra                      : in  std_logic_vector (10 downto 0);
            dia                        : in  std_logic_vector (7 downto 0);
            doa                        : out std_logic_vector (7 downto 0);
            dopa                       : out std_logic_vector (0 downto 0);
            web, enb, ssrb, clkb       : in  std_logic;
            dipb                       : in std_logic_vector (0 downto 0);
            addrb                      : in  std_logic_vector (10 downto 0);
            dib                        : in  std_logic_vector (7 downto 0);
            dob                        : out std_logic_vector (7 downto 0);
            dopb                       : out std_logic_vector (0 downto 0));
    end component;
    
begin  -- structure

    fifo_bram: ramb16_s9_s9
        port map (
            wea   => wr,
            ena   => '1',
            ssra  => reset,
            clka  => wr_clk,
            addra => wr_addr,
            dia   => wr_data,
            dipa  => "0",
            doa   => open,
            dopa  => open,
            web   => '0',
            enb   => rd,
            ssrb  => reset,
            clkb  => rd_clk,
            dipb  => "0",
            addrb => rd_addr,
            dib   => "00000000",
            dob   => rd_data,
            dopb  => open
            );

end structure;