ch_fifo.par

it describe how to develop the field programmable gate array

Release 5.1i - Par F.22
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.


SJC-XILIADM2::  Thu Jul 11 11:34:58 2002


Y:/XILI/QualityPartnerBuild3/bin/nt/par.exe -w -ol 2 -t 1 ch_fifo_map.ncd
ch_fifo.ncd ch_fifo.pcf 


Constraints file: ch_fifo.pcf

Loading device database for application par from file "ch_fifo_map.ncd".
   "ch_fifo" is an NCD, version 2.37, device xc2v40, package fg256, speed -4
Loading device for application par from file '2v40.nph' in environment
Y:/XILI/QualityPartnerBuild3.
The STEPPING level for this design is 1.
Device speed data version:  ADVANCED 1.108 2002-06-12.


Resolved that DCM <inst_mydcm_dcm_inst> must be placed at site DCM_X1Y1.
Resolved that RAMB16 <fifo_2048x8_inst_fifo_bram> must be placed at site
RAMB16_X1Y1.


Device utilization summary:

   Number of External IOBs            17 out of 88     19%
      Number of LOCed External IOBs    0 out of 17      0%

   Number of RAMB16s                   1 out of 4      25%
   Number of SLICEs                  174 out of 256    67%

   Number of BUFGMUXs                  2 out of 16     12%
   Number of DCMs                      1 out of 4      25%



Overall effort level (-ol):   2 (set by user)
Placer effort level (-pl):    2 (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    2 (set by user)


Phase 1.1
Phase 1.1 (Checksum:989c16) REAL time: 2 secs 

Phase 3.23
......................
Phase 3.23 (Checksum:989682) REAL time: 2 secs 

Phase 4.3
Phase 4.3 (Checksum:26259fc) REAL time: 3 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 3 secs 

Phase 6.8
.....................................
.............................................
Phase 6.8 (Checksum:9af43d) REAL time: 3 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 3 secs 

Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 3 secs 

Phase 9.24
Phase 9.24 (Checksum:55d4a77) REAL time: 3 secs 

Writing design to file ch_fifo.ncd.

Total REAL time to Placer completion: 3 secs 
Total CPU time to Placer completion: 3 secs 


Starting Router          REAL time: 3 secs 

Phase 1: 1080 unrouted;       REAL time: 3 secs 

Phase 2: 984 unrouted;       REAL time: 3 secs 

Phase 3: 275 unrouted;       REAL time: 3 secs 

Phase 4: 0 unrouted;       REAL time: 4 secs 

Finished Router          REAL time: 4 secs 

Total REAL time to Router completion: 4 secs 
Total CPU time to Router completion: 3 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Max Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|            wr_clk          |  Global  |   28   |  0.206     |  0.656      |
+----------------------------+----------+--------+------------+-------------+
|            rd_clk          |  Global  |   27   |  0.205     |  0.655      |
+----------------------------+----------+--------+------------+-------------+


   The Delay Summary Report

   The Score for this design is: 127


The Number of signals not completely routed for this design is: 0

   The Average Connection Delay for this design is:        0.802 ns
   The Maximum Pin Delay is:                               2.992 ns
   The Average Connection Delay on the 10 Worst Nets is:   2.351 ns

   Listing Pin Delays by value: (ns)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
         747         281          52           0           0           0


All signals are completely routed.

Total REAL time to PAR completion: 6 secs 
Total CPU time to PAR completion: 4 secs 

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file ch_fifo.ncd.


PAR done.