ch_fifo_pack.vhd

来自「it describe how to develop the field pro」· VHDL 代码 · 共 50 行

library ieee;
use ieee.std_logic_1164.all;

package ch_fifo_pack is

    function or_reduce (
        slv : std_logic_vector)
        return std_logic;

        function and_reduce (
        slv : std_logic_vector)
        return std_logic;

        function xor_reduce (
        slv : std_logic_vector)
        return std_logic;

end ch_fifo_pack;

package body ch_fifo_pack is
        
    function or_reduce (slv : std_logic_vector) return std_logic is
        variable result : std_logic := '0';
    begin
        for i in slv'range loop
            result := result or slv(i);
        end loop;
        return result;
    end function or_reduce;

    function and_reduce (slv : std_logic_vector) return std_logic is
        variable result : std_logic := '1';
    begin
        for i in slv'range loop
            result := result and slv(i);
        end loop;
        return result;
    end function and_reduce;

    function xor_reduce (slv : std_logic_vector) return std_logic is
        variable result : std_logic := '0';
    begin
        for i in slv'range loop
            result := result xor slv(i);
        end loop;
        return result;
    end function xor_reduce;
    
end ch_fifo_pack;