vhdllib.ref

it describe how to develop the field programmable gate array

	ch_fifo_pack	NULL	W:/marial/v5/labs/flow/./vhdl/ch_fifo_pack.vhd	sub00/vhpl00
	ch_fifo_pack	ch_fifo_pack	W:/marial/v5/labs/flow/./vhdl/ch_fifo_pack.vhd	sub00/vhpl01
	mydcm	NULL	W:/marial/v5/labs/flow/MyDCM.vhd	sub00/vhpl02
	mydcm	struct	W:/marial/v5/labs/flow/MyDCM.vhd	sub00/vhpl03
	pn_correlation	NULL	W:/marial/v5/labs/flow/./vhdl/pn_correlation.vhd	sub00/vhpl04
	pn_correlation	rtl	W:/marial/v5/labs/flow/./vhdl/pn_correlation.vhd	sub00/vhpl05
	pn_correlation_fsm	NULL	W:/marial/v5/labs/flow/./vhdl/pn_correlation_fsm.vhd	sub00/vhpl06
	pn_correlation_fsm	rtl	W:/marial/v5/labs/flow/./vhdl/pn_correlation_fsm.vhd	sub00/vhpl07
	pn_correlator	NULL	W:/marial/v5/labs/flow/./vhdl/pn_correlator.vhd	sub00/vhpl08
	pn_correlator	structure	W:/marial/v5/labs/flow/./vhdl/pn_correlator.vhd	sub00/vhpl09
	fifo_status	NULL	W:/marial/v5/labs/flow/./vhdl/fifo_status.vhd	sub00/vhpl10
	fifo_status	rtl	W:/marial/v5/labs/flow/./vhdl/fifo_status.vhd	sub00/vhpl11
	fifo_2048x8	NULL	W:/marial/v5/labs/flow/./vhdl/fifo_2048x8.vhd	sub00/vhpl12
	fifo_2048x8	structure	W:/marial/v5/labs/flow/./vhdl/fifo_2048x8.vhd	sub00/vhpl13
	ch_fifo	NULL	W:/marial/v5/labs/flow/./vhdl/ch_fifo.vhd	sub00/vhpl14
	ch_fifo	structure	W:/marial/v5/labs/flow/./vhdl/ch_fifo.vhd	sub00/vhpl15