flowlabtc.npl

it describe how to develop the field programmable gate array

JDF F
// Created by Project Navigator ver 1.0
PROJECT FlowLab
DESIGN flowlabtc Normal
DEVFAM virtex2
DEVFAMTIME 0
DEVICE xc2v40
DEVICETIME 0
DEVPKG fg256
DEVPKGTIME 0
DEVSPEED -4
DEVSPEEDTIME 0
FLOW XST VHDL
FLOWTIME 0
MODULE fifo_2048x8.vhd
MODSTYLE fifo_2048x8 Normal
MODULE pn_correlation.vhd
MODSTYLE pn_correlation Normal
MODULE pn_correlation_fsm.vhd
MODSTYLE pn_correlation_fsm Normal
MODULE fifo_status.vhd
MODSTYLE fifo_status Normal
MODULE MyDCM.xaw
MODSTYLE MyDCM Normal
MODULE ch_fifo.vhd
MODSTYLE ch_fifo Normal
MODULE pn_correlator.vhd
MODSTYLE pn_correlator Normal
LIBFILE ch_fifo_pack.vhd work ***
DEPASSOC ch_fifo myucf.ucf SYSTEM
[STRATEGY-LIST]
Normal=True