ch_fifo.bld

it describe how to develop the field programmable gate array

Release 5.1i - ngdbuild F.22
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild -quiet -dd w:\marial\v5\labs\flow\verilog/_ngo -uc
myucf.ucf -insert_keep_hierarchy -p xc2v40-fg256-4 ch_fifo.ngc ch_fifo.ngd 

Reading NGO file "W:/marial/v5/labs/flow/verilog/ch_fifo.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "myucf.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "ch_fifo.ngd" ...

Writing NGDBUILD log file "ch_fifo.bld"...