myucf.lfp

it describe how to develop the field programmable gate array

# begin LFP file W:\marial\v5\labs\flow\verilog\myucf.lfp
designfile ch_fifo.ngd
INST "pn_correlator_inst_pn_correlation_fsm_inst_Madd__n0005_inst_cy_35" COLOR=7  ;
INST "fifo_status_inst_wr_addr_inst_cy_12" COLOR=8  ;
INST "fifo_status_inst_rd_addr_inst_cy_1" COLOR=9  ;
INST "fifo_status_inst_Msub__n0016_inst_cy_24" COLOR=10  ;
INST "ch_fifo" COLOR=11  ;