pn_correlation_fsm.v

it describe how to develop the field programmable gate array

module pn_correlation_fsm(clk, reset, pn_fnd, pn_lock, pn_acq, wr, wr_addr_srst);
    input clk, reset, pn_fnd;
    output wr_addr_srst;
    output pn_lock, pn_acq, wr;
    reg    pn_acq, wr;

    reg [3:0]   cs, ns;
    reg [10:0] pn_addr_cntr;
    reg [2:0]  eight_cnt;
    wire       eight_cnt_tc;
    integer    j, k;
    reg        pn_acq_q0;
    
    parameter [3:0] init = 4'b0001, 
		    pn_search = 4'b0010, 
		    pn_fnd1 = 4'b0100,
		    locked = 4'b1000;
    
    always @ (posedge clk or posedge reset)
    begin
	if (reset)
	  cs <= init;
	else
	  cs <= ns;
    end // always @ (posedge clk or posedge reset)

    //_____________________________________________________________________
    // pn_correlation_fsm
    //_____________________________________________________________________
    always @ (cs or pn_fnd or pn_addr_cntr or eight_cnt_tc or pn_acq_q0)
    begin: pn_cor_fsm
	// default
	ns = cs;

	case (cs)
	    init:
	      ns = pn_search;
	    pn_search:
	      if (pn_fnd)
		ns = pn_fnd1;
	    pn_fnd1:
	      if (pn_fnd & pn_acq_q0 & pn_addr_cntr != 0)
		ns = locked;
	      else if (~pn_fnd & pn_acq_q0 & pn_addr_cntr != 0)
		ns = pn_search;
	    locked:
		if (~pn_fnd & pn_acq_q0)
		  ns = pn_search;
	    default:
	      ns = init;
	endcase // case(cs)
    end // block: pn_cor_fsm

    // Assign output pn_lock
    assign pn_lock = (cs == locked) ? 1 : 0;
    assign wr_addr_srst = (cs == pn_search) ? 1:0;

    //_____________________________________________________________________
    // Count eight clock cycles.  After eight clock cycles, tc = 1 which enables
    // the writing of data into fifo (once a pn_fnd is true) and enables the big
    // counter which counts through 256 8bit data samples.  After every 256 8bit
    // data samples, pn is searched for.
    //_____________________________________________________________________
    assign eight_cnt_tc = &eight_cnt;
    always @ (posedge clk or posedge reset)
    begin: count_eight_bits
	if (reset)
	  eight_cnt <= 0;
	else
	begin
	    // default
	    eight_cnt <= 0;
	    
	    case (ns)
		pn_search:
		  if (pn_fnd)
		    eight_cnt <= eight_cnt + 1;
		pn_fnd1, locked:
		  eight_cnt <= eight_cnt + 1;
	    endcase // case(ns)
	end // else: !if(reset)
    end // block: count_eight_bits
	      
    //_____________________________________________________________________
    // Create pn_addr_cntr which counts the number of clock cycles since the
    // first pn_fnd occured.  This address indicates the locations where the
    // next pn should be found.
    //_____________________________________________________________________
    always @ (posedge clk or posedge reset)
    begin: create_pn_addr_cntr
	if (reset)
	  pn_addr_cntr <= 0;
	else
	begin
	    // default
	    
	    case (ns)
		pn_search:
		  if (pn_fnd)
		    pn_addr_cntr <= pn_addr_cntr + 1;
		  else
		    pn_addr_cntr <= 0;
		pn_fnd1, locked:
		  if (eight_cnt_tc)
		    pn_addr_cntr <= pn_addr_cntr + 1;
		default:
		  pn_addr_cntr <= 0;
	    endcase // case(ns)
	end // else: !if(reset)
    end // block: create_pn_addr_cntr

    //_____________________________________________________________________
    // Create pn_acq signal to indicate to the pn_correlator to search for pn
    //_____________________________________________________________________
    always @ (posedge clk or posedge reset)
    begin: create_pn_acq
	if (reset)
	begin
	    pn_acq <= 0;
	    pn_acq_q0 <= 0;
	end
	else
	begin
	    // default
	    pn_acq <= 0;
	    pn_acq_q0 <= pn_acq;
	    for (j = 0; j <= 8; j = j + 1)
	      if (j == 0 & cs == pn_fnd1) // this prevents the fsm from looking for a pn on two consecutive 8bit samples
		pn_acq <= 0;
	      else if ((pn_addr_cntr == (j*256 -1) & eight_cnt == 6) | ns == pn_search) // enable pn_acq 2 clock cycles before search is to begin
		pn_acq <= 1;
	end // else: !if(reset)
    end // block: create_pn_acq

    //_____________________________________________________________________
    // Create wr signal for fifo
    //_____________________________________________________________________
    always @ (posedge clk or posedge reset)
    begin: create_wr
	if (reset)
	  wr <= 0;
	else
	begin
	    // defalut
	    wr <= 0;
	    if (eight_cnt == 6) // enabled only every 8 clock cycles (clock enable = eight_cnt_tc)
	    begin
		// default
		wr <= 1;
		for (k = 0; k <= 8; k = k + 1)
		  if (pn_addr_cntr == k*256 - 1) // disable when it is time to look for PN code
		    wr <= 0;
	    end // if (eight_cnt == 6)
	end // else: !if(reset)
    end // block: create_wr
    
endmodule // pn_correlation_fsm