devctrl.inc

TI DSP系列读下CF卡程序,可用做图象存储产品的开发

IF !DEFINED (_DEVCTRL_)

_DEVCTRL_ EQU  1



;-----------------------------------------------------------------------------
; MEM2 control register
; Access timing
MEM2_CR_ADDRESS_SETUP_TIME       EQU (%11<<8)
MEM2_CR_ACCESS_TIME              EQU (%111<<5)
MEM2_CR_DATA_BUS_HOLD_TIME       EQU (%11<<3)
; Address
MEM2_CR_ADDR                     EQU ((%1<<21|%000<<13)         | \
                                    MEM2_CR_ADDRESS_SETUP_TIME  | \
		                            MEM2_CR_ACCESS_TIME         | \
		                            MEM2_CR_DATA_BUS_HOLD_TIME)

; data bit positions for MEM2 control register
PCMCIA_EN                        EQU (1<<0)
SMARTM_EN                        EQU (1<<1)
DPRAM_EN                         EQU (1<<2)
SENSOR_EN                        EQU (1<<3)


ENABLE_SENSOR MACRO Reg
            MOVI     \Reg, SENSOR_EN
            STW.IOA  0, \Reg, MEM2_CR_ADDR
            ENDMACRO ENABLE_SENSOR

ENABLE_PCMCIA MACRO Reg
            MOVI     \Reg, PCMCIA_EN
            STW.IOA  0, \Reg, MEM2_CR_ADDR
            ENDMACRO ENABLE_PCMCIA

ENABLE_SMARTM MACRO Reg
            MOVI     \Reg, SMARTM_EN
            STW.IOA  0, \Reg, MEM2_CR_ADDR
            ENDMACRO ENABLE_SMARTM

ENABLE_DPRAM MACRO Reg
            MOVI     \Reg, DPRAM_EN
            STW.IOA  0, \Reg, MEM2_CR_ADDR
            ENDMACRO ENABLE_DPRAM

DISABLE_MEM2 MACRO
            STW.IOA  0, 0, MEM2_CR_ADDR
            ENDMACRO DISABLE_MEM2

;-----------------------------------------------------------------------------



;-----------------------------------------------------------------------------
; Wait pin control register
; Access timing
WAIT_CR_ADDRESS_SETUP_TIME       EQU (%11<<8)
WAIT_CR_ACCESS_TIME              EQU (%111<<5)
WAIT_CR_DATA_BUS_HOLD_TIME       EQU (%11<<3)
; Address
WAIT_CR_ADDR                     EQU ((%1<<21|%010<<13)         | \
                                    WAIT_CR_ADDRESS_SETUP_TIME  | \
		                            WAIT_CR_ACCESS_TIME         | \
		                            WAIT_CR_DATA_BUS_HOLD_TIME)

; data bit positions for WAIT control register
SONY_NP                          EQU (1<<0)
CARRIER                          EQU (1<<1)
SENSOR_WEN                       EQU (1<<2)


ENABLE_SENSOR_WEN MACRO Reg
            LDW.IOA  0, \Reg, WAIT_CR_ADDR
            ORI      \Reg, SENSOR_WEN
            STW.IOA  0, \Reg, WAIT_CR_ADDR
            ENDMACRO ENABLE_SENSOR_WEN

ENABLE_PCMCIA_WEN MACRO Reg
            LDW.IOA  0, \Reg, WAIT_CR_ADDR
            ANDNI    \Reg, SENSOR_WEN
            STW.IOA  0, \Reg, WAIT_CR_ADDR
            ENDMACRO ENABLE_PCMCIA_WEN
;-----------------------------------------------------------------------------



;-----------------------------------------------------------------------------
; USB and SmartMedia Control Register
; Access timing
SM_CR_ADDRESS_SETUP_TIME         EQU (%11<<8)
SM_CR_ACCESS_TIME                EQU (%111<<5)
SM_CR_DATA_BUS_HOLD_TIME         EQU (%11<<3)
; Address
SM_CR_ADDR                       EQU ((%1<<21|%011<<13)          | \
                                       SM_CR_ADDRESS_SETUP_TIME  | \
		                       SM_CR_ACCESS_TIME         | \
		                       SM_CR_DATA_BUS_HOLD_TIME)

; data bit positions for USB and SmartMedia control register
SUSP_DIR                         EQU (1<<0)
USB_SUSP                         EQU (1<<1)
SMWP_                            EQU (1<<2)

SET_WRITABLE MACRO Reg
            LDW.IOA  0, \Reg, SM_CR_ADDR
            ORI      \Reg, SMWP_
            STW.IOA  0, \Reg, SM_CR_ADDR
            ENDMACRO SET_WRITABLE

SET_WRITE_PROTECT MACRO Reg
            LDW.IOA  0, \Reg, SM_CR_ADDR
            ANDNI    \Reg, SMWP_
            STW.IOA  0, \Reg, SM_CR_ADDR
            ENDMACRO SET_WRITE_PROTECT

;-----------------------------------------------------------------------------



;-----------------------------------------------------------------------------
; Latch for LEDs, keys, general I/O and image sensor
; Access timing
LATCH_ADDRESS_SETUP_TIME         EQU (%00<<8)
LATCH_ACCESS_TIME                EQU (%001<<5)
LATCH_DATA_BUS_HOLD_TIME         EQU (%00<<3)
; Address
LATCH_ADDR                       EQU ((%1<<21|%111<<13)          | \
                                      LATCH_ADDRESS_SETUP_TIME   | \
		                              LATCH_ACCESS_TIME          | \
		                              LATCH_DATA_BUS_HOLD_TIME)

LatchReg                         EQU <G10>       ; LatchReg holds content of latch

; latch data bit positions for Hewlett-Packard HDCS-2000 image sensor
HP_TCLK                          EQU (1<<0)
HP_RXD                           EQU (1<<1)
HP_TXD                           EQU (1<<0)
HP_RESET_                        EQU (1<<2)
HP_STBY_                         EQU (1<<3)

PCD1				 EQU (1<<6)
PCD2				 EQU (1<<7)

KEY0                             EQU (1<<8)
KEY1                             EQU (1<<9)
KEY2                             EQU (1<<10)
KEY3                             EQU (1<<11)
KEY4                             EQU (1<<12)
KEY5                             EQU (1<<13)
KEY6                             EQU (1<<14)
KEY7                             EQU (1<<15)


;-----------------------------------------------------------------------------



;-----------------------------------------------------------------------------
; Hewlett-Packard HDCS-2000 image sensor control register
; Access timing
HP_CR_ADDRESS_SETUP_TIME         EQU (%11<<8)
HP_CR_ACCESS_TIME                EQU (%111<<5)
HP_CR_DATA_BUS_HOLD_TIME         EQU (%11<<3)
; Address
HP_CR_ADDR                       EQU ((%1<<21|%001<<13)         | \
                                      HP_CR_ADDRESS_SETUP_TIME  | \
		                              HP_CR_ACCESS_TIME         | \
		                              HP_CR_DATA_BUS_HOLD_TIME)

; data bit positions for Hewlett-Packard HDCS-2000 image sensor control register
HP_WAITC1                        EQU (1<<0)
HP_WAITC2                        EQU (1<<1)
HP_CLOCK1                        EQU (1<<2)
HP_CLOCK2                        EQU (1<<3)
;-----------------------------------------------------------------------------


HP_DATA_ADDR                     EQU $8000_0000



DUMMY_IO_ADDRESS_SETUP_TIME       EQU (%00<<8)
DUMMY_IO_ACCESS_TIME              EQU (%000<<5)
DUMMY_IO_DATA_BUS_HOLD_TIME       EQU (%00<<3)
; Address
DUMMY_IO_ADDR                     EQU DUMMY_IO_ADDRESS_SETUP_TIME  | \
		                              DUMMY_IO_ACCESS_TIME         | \
		                              DUMMY_IO_DATA_BUS_HOLD_TIME


ENDIF