spi-prt.txt

昨天在论坛上看到有人帖出了他写的并串转换VHDL代码

module ptosda(clk,rst,sp,dataack);

input clk,rst,sp;  
inout ack;
input [7:0] data;

reg [3:0] state_out;
reg [7:0] databuf;

wire [7:0] data;

parameter bing=1'b0,
         chuan=1'0;
parameter bit0=4'b0000,
          bit1=4'b0001,
          bit2=4'b0010,
          bit3=4'b0011,
          bit4=4'b0100,
          bit5=4'b0101,
          bit6=4'b0110,
          bit7=4'b0111,
          idel=4'b1000;

assign data[7]=link_write?databuf[7]:1'bz;
assign data=link_write?databuf:8'bz;

always@(posedge clk)
  begin
   if(!rst)
    
    begin
     ack <= 0;
     link_write <=0;
     state_out <= idle;
     databuf <= 0;
    end

   else

    begin
      case(sp)
       bing:
        begin
         if(finish_flag == 0)
           begin
            DtoS;
           end
          else
           begin
             state_out <= idel;
             databuf <= data;
             finish_flag = 0;
            end
          end
        chuan:
         begin
           if(finish_flag == 0)
            begin
              StoD;
            end
           else
            begin
            state_out <= idel;
            finish_flag = 0;
            end
         endcase
        end
       end
task StoD;
  begin
    case(state_out)
      idle:
       begin
        link_write <= 0;
        ack <= 1;
        databuf[7] <= data[7];
        databuf <= databuf>>1;
        state_out <= bit7;
       end
    bit7:
     begin
       ack <=1;
        databuf[7] <= data[7];
        databuf <= databuf>>1;
        state_out <= bit6;
       end
    bit6:
     begin
       ack <=1;
        databuf[7] <= data[7];
        databuf <= databuf>>1;
        state_out <= bit5;
       end
    bit5:
     begin
       ack <=1;
        databuf[7] <= data[7];
        databuf <= databuf>>1;
        state_out <= bit4;
       end
    bit4:
     begin
       ack <=1;
        databuf[7] <= data[7];
        databuf <= databuf>>1;
        state_out <= bit3;
       end
    bit2:
     begin
       ack <=1;
        databuf[7] <= data[7];
        databuf <= databuf>>1;
        state_out <= bit1;
       end
    bit1:
     begin
        ack<=1;
        databuf[7] <= data[7];
        databuf <= databuf>>1;
        state_out <= bit0;
       end
    bit0:
     begin
       link_write <= 1;
       finish_flag=1;
       ack <= 0;
       state_out <= 4'b111;
       end
     
default:
    begin
     link_write <= 0;
     state_out <= 4'b111;
    end
   endcase
   end
endtask
task DtoS;
begin
   case(state_out)
   idle:
    begin
     link_write <=1;
     state_out <= bit7;
    end
  bit7:
   begin
    databuf <= databuf << 1;
    state_out <= bit6;
   end
  bit6:
   begin
    databuf <= databuf << 1;
    state_out <= bit5;
   end  
  bit5:
   begin
    databuf <= databuf << 1;
    state_out <= bit4;
   end  
  bit4:
   begin
    databuf <= databuf << 1;
    state_out <= bit3;
   end  
  bit3:
   begin
    databuf <= databuf << 1;
    state_out <= bit2;
   end  
  bit2:
   begin
    databuf <= databuf << 1;
    state_out <= bit1;
   end  
  bit1:
   begin
    databuf <= databuf << 1;
    state_out <= bit0;
   end  
  bit0:
   begin
     link_write <= 0;
     finish_flag = 1;
     ack <= 1;
     state_out <= 4'b1111;
   end
  default:
   begin
     link_write <= 0;
     state_out <= 4'b1111;
   end
  endcase
end  
endtask
endmodule