📄 rtl8139.inc
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;; RTL8139.INC ;;;; ;;;; Ethernet driver for Menuet OS ;;;; ;;;; Version 0.2 11 August 2003 ;;;; ;;;; Driver for chips of RealTek 8139 family ;;;; References: ;;;; www.realtek.com.hw - data sheets ;;;; rtl8139.c - linux driver ;;;; 8139too.c - linux driver ;;;; ethernet driver template by Mike Hibbett ;;;; ;;;; The copyright statement is ;;;; ;;;; GNU GENERAL PUBLIC LICENSE ;;;; Version 2, June 1991 ;;;; ;;;; Copyright 2003 Endre Kozma, ;;;; endre.kozma@axelero.hu ;;;; ;;;; See file COPYING for details ;;;; ;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ETH_ALEN equ 6 ETH_HLEN equ (2 * ETH_ALEN + 2) ETH_ZLEN equ 60 ; 60 + 4bytes auto payload for ; mininmum 64bytes frame length PCI_REG_COMMAND equ 0x04 ; command register PCI_BIT_PIO equ 0 ; bit0: io space control PCI_BIT_MMIO equ 1 ; bit1: memory space control PCI_BIT_MASTER equ 2 ; bit2: device acts as a PCI master RTL8139_REG_MAR0 equ 0x08 ; multicast filter register 0 RTL8139_REG_MAR4 equ 0x0c ; multicast filter register 4 RTL8139_REG_TSD0 equ 0x10 ; transmit status of descriptor RTL8139_REG_TSAD0 equ 0x20 ; transmit start address of descriptor RTL8139_REG_RBSTART equ 0x30 ; RxBuffer start address RTL8139_REG_COMMAND equ 0x37 ; command register RTL8139_REG_CAPR equ 0x38 ; current address of packet read RTL8139_REG_IMR equ 0x3c ; interrupt mask register RTL8139_REG_ISR equ 0x3e ; interrupt status register RTL8139_REG_TXCONFIG equ 0x40 ; transmit configuration register RTL8139_REG_TXCONFIG_0 equ 0x40 ; transmit configuration register 0 RTL8139_REG_TXCONFIG_1 equ 0x41 ; transmit configuration register 1 RTL8139_REG_TXCONFIG_2 equ 0x42 ; transmit configuration register 2 RTL8139_REG_TXCONFIG_3 equ 0x43 ; transmit configuration register 3 RTL8139_REG_RXCONFIG equ 0x44 ; receive configuration register 0 RTL8139_REG_RXCONFIG_0 equ 0x44 ; receive configuration register 0 RTL8139_REG_RXCONFIG_1 equ 0x45 ; receive configuration register 1 RTL8139_REG_RXCONFIG_2 equ 0x46 ; receive configuration register 2 RTL8139_REG_RXCONFIG_3 equ 0x47 ; receive configuration register 3 RTL8139_REG_MPC equ 0x4c ; missed packet counter RTL8139_REG_9346CR equ 0x50 ; serial eeprom 93C46 command register RTL8139_REG_CONFIG1 equ 0x52 ; configuration register 1 RTL8139_REG_CONFIG4 equ 0x5a ; configuration register 4 RTL8139_REG_HLTCLK equ 0x5b ; undocumented halt clock register RTL8139_REG_BMCR equ 0x62 ; basic mode control register RTL8139_REG_ANAR equ 0x66 ; auto negotiation advertisement register; 5.1 packet header RTL8139_BIT_RUNT equ 4 ; total packet length < 64 bytes RTL8139_BIT_LONG equ 3 ; total packet length > 4k RTL8139_BIT_CRC equ 2 ; crc error occured RTL8139_BIT_FAE equ 1 ; frame alignment error occured RTL8139_BIT_ROK equ 0 ; received packet is ok; 5.4 command register RTL8139_BIT_RST equ 4 ; reset bit RTL8139_BIT_RE equ 3 ; receiver enabled RTL8139_BIT_TE equ 2 ; transmitter enabled RTL8139_BIT_BUFE equ 0 ; rx buffer is empty, no packet stored; 5.6 interrupt status register RTL8139_BIT_ISR_TOK equ 2 ; transmit ok RTL8139_BIT_ISR_RER equ 1 ; receive error interrupt RTL8139_BIT_ISR_ROK equ 0 ; receive ok; 5.7 transmit configyration register RTL8139_BIT_TX_MXDMA equ 8 ; Max DMA burst size per Tx DMA burst RTL8139_BIT_TXRR equ 4 ; Tx Retry count 16+(TXRR*16); 5.8 receive configuration register RTL8139_BIT_RXFTH equ 13 ; Rx fifo threshold RTL8139_BIT_RBLEN equ 11 ; Ring buffer length indicator RTL8139_BIT_RX_MXDMA equ 8 ; Max DMA burst size per Rx DMA burst RTL8139_BIT_NOWRAP equ 7 ; transfered data wrapping RTL8139_BIT_9356SEL equ 6 ; eeprom selector 9346/9356 RTL8139_BIT_AER equ 5 ; accept error packets RTL8139_BIT_AR equ 4 ; accept runt packets RTL8139_BIT_AB equ 3 ; accept broadcast packets RTL8139_BIT_AM equ 2 ; accept multicast packets RTL8139_BIT_APM equ 1 ; accept physical match packets RTL8139_BIT_AAP equ 0 ; accept all packets; 5.9 93C46/93C56 command register RTL8139_BIT_93C46_EEM1 equ 7 ; RTL8139 eeprom operating mode1 RTL8139_BIT_93C46_EEM0 equ 6 ; RTL8139 eeprom operating mode0 RTL8139_BIT_93C46_EECS equ 3 ; chip select RTL8139_BIT_93C46_EESK equ 2 ; serial data clock RTL8139_BIT_93C46_EEDI equ 1 ; serial data input RTL8139_BIT_93C46_EEDO equ 0 ; serial data output; 5.11 configuration register 1 RTL8139_BIT_LWACT equ 4 ; see RTL8139_REG_CONFIG1 RTL8139_BIT_SLEEP equ 1 ; sleep bit at older chips RTL8139_BIT_PWRDWN equ 0 ; power down bit at older chips RTL8139_BIT_PMEn equ 0 ; power management enabled; 5.14 configuration register 4 RTL8139_BIT_LWPTN equ 2 ; see RTL8139_REG_CONFIG4; 6.2 transmit status register RTL8139_BIT_ERTXTH equ 16 ; early TX threshold RTL8139_BIT_TOK equ 15 ; transmit ok RTL8139_BIT_OWN equ 13 ; tx DMA operation is completed; 6.18 basic mode control register RTL8139_BIT_ANE equ 12 ; auto negotiation enable; 6.20 auto negotiation advertisement register RTL8139_BIT_TXFD equ 8 ; 100base-T full duplex RTL8139_BIT_TX equ 7 ; 100base-T RTL8139_BIT_10FD equ 6 ; 10base-T full duplex RTL8139_BIT_10 equ 5 ; 10base-T RTL8139_BIT_SELECTOR equ 0 ; binary encoded selector CSMA/CD=00001; RX/TX buffer size RTL8139_RBLEN equ 0 ; 0==8K 1==16k 2==32k 3==64k RTL8139_RX_BUFFER_SIZE equ (8192 shl RTL8139_RBLEN) MAX_ETH_FRAME_SIZE equ 1516 ; exactly 1514 wthout CRC RTL8139_NUM_TX_DESC equ 4 RTL8139_TX_BUFFER_SIZE equ (MAX_ETH_FRAME_SIZE * RTL8139_NUM_TX_DESC) RTL8139_TXRR equ 8 ; total retries = 16+(TXRR*16) RTL8139_TX_MXDMA equ 6 ; 0==16 1==32 2==64 3==128 ; 4==256 5==512 6==1024 7==2048 RTL8139_ERTXTH equ 8 ; in unit of 32 bytes e.g:(8*32)=256 RTL8139_RX_MXDMA equ 7 ; 0==16 1==32 2==64 3==128 ; 4==256 5==512 6==1024 7==unlimited RTL8139_RXFTH equ 7 ; 0==16 1==32 2==64 3==128 ; 4==256 5==512 6==1024 7==no threshold RTL8139_RX_CONFIG equ ((RTL8139_RBLEN shl RTL8139_BIT_RBLEN) \ or (RTL8139_RX_MXDMA shl RTL8139_BIT_RX_MXDMA) \ or (1 shl RTL8139_BIT_NOWRAP) \ or (RTL8139_RXFTH shl RTL8139_BIT_RXFTH) \ or (1 shl RTL8139_BIT_AB) or (1 shl RTL8139_BIT_APM) \ or (1 shl RTL8139_BIT_AER) or (1 shl RTL8139_BIT_AR) \ or (1 shl RTL8139_BIT_AM)) RTL8139_TX_TIMEOUT equ 30 ; 300 milliseconds timeout EE_93C46_REG_ETH_ID equ 7 ; MAC offset EE_93C46_READ_CMD equ (6 shl 6) ; 110b + 6bit address EE_93C56_READ_CMD equ (6 shl 8) ; 110b + 8bit address EE_93C46_CMD_LENGTH equ 9 ; start bit + cmd + 6bit address EE_93C56_CMD_LENGTH equ 11 ; start bit + cmd + 8bit ddress VER_RTL8139 equ 1100000b VER_RTL8139A equ 1110000b; VER_RTL8139AG equ 1110100b VER_RTL8139B equ 1111000b VER_RTL8130 equ VER_RTL8139B VER_RTL8139C equ 1110100b VER_RTL8100 equ 1111010b VER_RTL8100B equ 1110101b VER_RTL8139D equ VER_RTL8100B VER_RTL8139CP equ 1110110b VER_RTL8101 equ 1110111b IDX_RTL8139 equ 0 IDX_RTL8139A equ 1 IDX_RTL8139B equ 2 IDX_RTL8139C equ 3 IDX_RTL8100 equ 4 IDX_RTL8139D equ 5 IDX_RTL8139D equ 6 IDX_RTL8101 equ 7; These two must be 4 byte aligned ( which they are )rtl8139_rx_buff equ eth_data_startrtl8139_tx_buff equ rtl8139_rx_buff + (RTL8139_RX_BUFFER_SIZE + MAX_ETH_FRAME_SIZE) align 4rtl8139_rx_buff_offset: dd 0curr_tx_desc: dd 0hw_ver_array: db VER_RTL8139, VER_RTL8139A, VER_RTL8139B, VER_RTL8139C db VER_RTL8100, VER_RTL8139D, VER_RTL8139CP, VER_RTL8101HW_VER_ARRAY_SIZE = $-hw_ver_arrayhw_ver_id: db 0;***************************************************************************; Function; rtl8139_probe; Description; Searches for an ethernet card, enables it and clears the rx buffer; If a card was found, it enables the ethernet -> TCPIP link; Destroyed registers; eax, ebx, ecx, edx;;***************************************************************************rtl8139_probe:; enable the device mov al, 2 mov ah, [pci_bus] mov bh, [pci_dev] mov bl, PCI_REG_COMMAND call pci_read_reg mov cx, ax or cl, (1 shl PCI_BIT_MASTER) or (1 shl PCI_BIT_PIO) and cl, not (1 shl PCI_BIT_MMIO) mov al, 2 mov ah, [pci_bus] mov bh, [pci_dev] mov bl, PCI_REG_COMMAND call pci_write_reg; get chip version mov edx, [io_addr] add edx, RTL8139_REG_TXCONFIG_2 in ax, dx shr ah, 2 shr ax, 6 and al, 01111111b mov ecx, HW_VER_ARRAY_SIZE-1.chip_ver_loop: cmp al, [hw_ver_array+ecx] je .chip_ver_found dec ecx jns .chip_ver_loop xor cl, cl ; default RTL8139.chip_ver_found: mov [hw_ver_id], cl; wake up the chip mov edx, [io_addr] add edx, RTL8139_REG_HLTCLK mov al, 'R' ; run the clock out dx, al; unlock config and BMCR registers add edx, RTL8139_REG_9346CR - RTL8139_REG_HLTCLK mov al, (1 shl RTL8139_BIT_93C46_EEM1) or (1 shl RTL8139_BIT_93C46_EEM0) out dx, al; enable power management add edx, RTL8139_REG_CONFIG1 - RTL8139_REG_9346CR in al, dx cmp byte [hw_ver_id], IDX_RTL8139B jl .old_chip; set LWAKE pin to active high (default value).; it is for Wake-On-LAN functionality of some motherboards.; this signal is used to inform the motherboard to execute a wake-up process.; only at newer chips. or al, (1 shl RTL8139_BIT_PMEn) and al, not (1 shl RTL8139_BIT_LWACT) out dx, al add edx, RTL8139_REG_CONFIG4 - RTL8139_REG_CONFIG1 in al, dx and al, not (1 shl RTL8139_BIT_LWPTN) out dx, al jmp .finish_wake_up.old_chip:; wake up older chips and al, not ((1 shl RTL8139_BIT_SLEEP) or (1 shl RTL8139_BIT_PWRDWN)) out dx, al.finish_wake_up:; lock config and BMCR registers xor al, al mov edx, [io_addr] add edx, RTL8139_REG_9346CR out dx, al;***************************************************************************; Function; rt8139_reset; Description; Place the chip (ie, the ethernet card) into a virgin state; Destroyed registers; eax, ebx, ecx, edx;;***************************************************************************rtl8139_reset: mov edx, [io_addr] add edx, RTL8139_REG_COMMAND mov al, 1 shl RTL8139_BIT_RST out dx, al mov cx, 1000 ; wait no longer for the reset.wait_for_reset: in al, dx test al, 1 shl RTL8139_BIT_RST jz .reset_completed ; RST remains 1 during reset dec cx jns .wait_for_reset.reset_completed:; get MAC (hardware address) mov ecx, 2.mac_read_loop: lea eax, [EE_93C46_REG_ETH_ID+ecx] push ecx call rtl8139_read_eeprom pop ecx mov [node_addr+ecx*2], ax dec ecx jns .mac_read_loop; unlock config and BMCR registers⌨️ 快捷键说明
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